公开(公告)号：US20230178428A1

公开(公告)日：2023-06-08

申请号：US17543199

申请日：2021-12-06

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Fee Hoon Wendy Wong ,  Thomas Behrens ,  Eric Lopez Bonifacio ,  Chau Fatt Chiang ,  Irmgard Escher-Poeppel ,  Giovanni Ragasa Garbin ,  Martin Gruber ,  Tien Shyang Law ,  Mohamad Azian Mohamed Azizi ,  Si Hao Vincent Yeo

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/76838 ,  H01L21/563 ,  H01L23/31 ,  H01L21/4839

Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.

公开(公告)号：US10700037B2

公开(公告)日：2020-06-30

申请号：US15811375

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Eung San Cho ,  Thorsten Meyer ,  Xaver Schloegel ,  Thomas Behrens ,  Josef Hoeglauer

IPC: H01L23/00 ,  H01L23/498

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

公开(公告)号：US20220216173A1

公开(公告)日：2022-07-07

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US11069644B2

公开(公告)日：2021-07-20

申请号：US16556823

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US20210005557A1

公开(公告)日：2021-01-07

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US11264356B2

公开(公告)日：2022-03-01

申请号：US16842417

申请日：2020-04-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Andreas Grassmann ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

公开(公告)号：US20190148332A1

公开(公告)日：2019-05-16

申请号：US15811375

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Eung San Cho ,  Thorsten Meyer ,  Xaver Schloegel ,  Thomas Behrens ,  Josef Hoeglauer

IPC: H01L23/00 ,  H01L23/498

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

公开(公告)号：US11776927B2

公开(公告)日：2023-10-03

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

CPC classification number: H01L24/29 ,  B23K35/262 ,  C22C13/02 ,  H01L24/83 ,  H01L2224/2922 ,  H01L2224/29211 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29264 ,  H01L2224/29269 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US11502042B2

公开(公告)日：2022-11-15

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US10930614B2

公开(公告)日：2021-02-23

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred Mengel ,  Alexander Heinrich ,  Steffen Orso ,  Thomas Behrens ,  Oliver Eichinger ,  Lim Fong ,  Evelyn Napetschnig ,  Edmund Riedl

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.