公开(公告)号：US20230178428A1

公开(公告)日：2023-06-08

申请号：US17543199

申请日：2021-12-06

申请人： Infineon Technologies AG

发明人： Thorsten Meyer ,  Fee Hoon Wendy Wong ,  Thomas Behrens ,  Eric Lopez Bonifacio ,  Chau Fatt Chiang ,  Irmgard Escher-Poeppel ,  Giovanni Ragasa Garbin ,  Martin Gruber ,  Tien Shyang Law ,  Mohamad Azian Mohamed Azizi ,  Si Hao Vincent Yeo

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L21/76838 ,  H01L21/563 ,  H01L23/31 ,  H01L21/4839

摘要： A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.

公开(公告)号：US20230170329A1

公开(公告)日：2023-06-01

申请号：US17888669

申请日：2022-08-16

申请人： Infineon Technologies AG

发明人： Sock Chien Tey ,  Keck Tim Ang ,  Chan Lam Cha ,  Chau Fatt Chiang ,  Badrul Hisyam Ismail ,  Desmond Jenn Yong Loo ,  Ronizan Mohd Salleh ,  Norliza Morban ,  Si Hao Vincent Yeo ,  Chee Mun Wai ,  Fee Hoon Wendy Wong

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/4824 ,  H01L24/16 ,  H01L23/5386 ,  H01L24/32 ,  H01L21/568 ,  H01L25/50 ,  H01L2224/16157 ,  H01L2224/32145

摘要： A method of forming a semiconductor package includes providing a metal baseplate including a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US20230197585A1

公开(公告)日：2023-06-22

申请号：US17556341

申请日：2021-12-20

申请人： Infineon Technologies AG

发明人： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow ,  Khay Chwan Andrew Saw ,  Fee Hoon Wendy Wong

IPC分类号： H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L2224/211

摘要： A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.