公开(公告)号：US20170354040A1

公开(公告)日：2017-12-07

申请号：US15632216

申请日：2017-06-23

Applicant: Averatek Corporation

Inventor： Mihir Reddy ,  Michael Riley Vinson ,  Sunity K. Sharma

IPC: H05K3/18 ,  C23C18/16 ,  C23C18/00 ,  C23C18/32 ,  C23C18/30 ,  C23C18/20 ,  C23C18/18 ,  C23C18/38

CPC classification number: H05K3/184 ,  C23C18/00 ,  C23C18/1608 ,  C23C18/161 ,  C23C18/1817 ,  C23C18/1841 ,  C23C18/1844 ,  C23C18/1865 ,  C23C18/1889 ,  C23C18/1893 ,  C23C18/2033 ,  C23C18/208 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  H05K2203/0565 ,  H05K2203/125

Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

公开(公告)号：US09351402B2

公开(公告)日：2016-05-24

申请号：US14554334

申请日：2014-11-26

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K1/09 ,  H05K1/11 ,  H01L21/48 ,  H01L23/498 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H01L23/00

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.

公开(公告)号：US20150034366A1

公开(公告)日：2015-02-05

申请号：US14481188

申请日：2014-09-09

Applicant: Panasonic Corporation

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA ,  Hiromitsu TAKASHITA ,  Tsuyoshi TAKEDA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/119 ,  H01L2224/81385 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/0085 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0224 ,  H05K2201/0233 ,  H05K2201/0239 ,  H05K2201/0376 ,  H05K2201/0769 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09972 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/0143 ,  H05K2203/0228 ,  H05K2203/0264 ,  H05K2203/0285 ,  H05K2203/0565 ,  H05K2203/0706 ,  H05K2203/0776 ,  H05K2203/1163 ,  Y02P70/611

Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 μm or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.

Abstract translation: 本发明的一个方面涉及一种包括绝缘基底的电路板; 以及电路层，其由导体形成，并且设置在所述绝缘基底基板的表面上，其中所述绝缘基底具有表面粗糙度Ra为0.5μm以下的平滑表面，并且所述导体至少部分地 嵌入形成在绝缘性基板的表面的布线槽。

公开(公告)号：US20120285736A1

公开(公告)日：2012-11-15

申请号：US13494417

申请日：2012-06-12

Applicant: Shingo YOSHIOKA ,  Hiroaki FUJIWARA

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/023 ,  H05K1/0284 ,  H05K1/11 ,  H05K1/162 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/09381 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0108 ,  H05K2203/0565 ,  Y10T29/49114 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: The present invention relates to a method of producing a multilayer circuit board including: a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the film.

Abstract translation: 本发明涉及一种制造多层电路板的方法，包括：在绝缘基板的表面上形成可溶胀树脂膜的成膜步骤，形成电路槽的电路槽形成步骤，该电路槽的深度等于或等于 大于膜的外表面上的可溶胀树脂膜的厚度，在电路槽的表面和可溶胀树脂膜的表面上沉积电镀催化剂或其前体的催化剂沉积步骤， 分离步骤，用特定的液体使溶胀性树脂膜溶胀，然后从膨胀的基材表面分离溶胀的树脂膜;以及电镀处理步骤，仅在由镀催化剂或电镀催化剂形成的镀层催化剂的区域形成无电镀膜 电镀催化剂前体在分离膜后保持未分离。

公开(公告)号：US20090272564A1

公开(公告)日：2009-11-05

申请号：US12431950

申请日：2009-04-29

Applicant: Shingo YOSHIOKA ,  Hiroaki FUJIWARA

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/023 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/11 ,  H05K1/162 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/09381 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0108 ,  H05K2203/0565 ,  H05K2203/161 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.The method of producing a multilayer circuit board in an aspect of the present invention includes a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the swellable resin film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the swellable resin film.

公开(公告)号：US20090272562A1

公开(公告)日：2009-11-05

申请号：US12326169

申请日：2008-12-02

Applicant: Shingo YOSHIOKA ,  Hiroaki FUJIWARA

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K3/184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/023 ,  H05K1/0284 ,  H05K1/11 ,  H05K1/162 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/09381 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0108 ,  H05K2203/0565 ,  Y10T29/49114 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.The method of producing a multilayer circuit board in an aspect of the present invention includes a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the swellable resin film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the swellable resin film.

Abstract translation: 本发明的一个方面的目的是提供一种电路板的制造方法，其能够高精度地保存电路剖面，并且通过加法处理给出具有所需深度的电路以准备精细电路。 在本发明的一个方面中，制造多层电路板的方法包括：在绝缘性基板的表面上形成可溶胀树脂膜的成膜工序;形成电路槽的电路槽形成工序，其深度等于 或大于可溶胀树脂膜的外表面上的可溶胀树脂膜的厚度，在电路槽的表面和可溶胀树脂膜的表面上沉积电镀催化剂或其前体的催化剂沉积步骤， 使用特定液体使溶胀性树脂膜溶胀，然后将所述溶胀树脂膜与所述绝缘性基板表面分离的膜分离工序，以及仅在所述镀催化剂或所述镀层的区域形成无电镀膜的电镀处理工序 在可溶胀树脂膜分离之后，由电镀催化剂前体形成的催化剂保持未分离。

公开(公告)号：US20070218191A1

公开(公告)日：2007-09-20

申请号：US11680846

申请日：2007-03-01

Applicant: Hidemichi FURIHATA ,  Satoshi KIMURA ,  Toshihiko KANEDA ,  Takeshi KIJIMA

Inventor： Hidemichi FURIHATA ,  Satoshi KIMURA ,  Toshihiko KANEDA ,  Takeshi KIJIMA

IPC: B05D5/12

CPC classification number: H05K3/184 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/1692 ,  C23C18/1879 ,  C23C18/30 ,  C23C18/31 ,  C23C18/36 ,  H05K3/24 ,  H05K2203/0565 ,  H05K2203/072 ,  H05K2203/088 ,  H05K2203/1476

Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) exposing a top surface of the substrate to steam; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.

Abstract translation: 提供一种通过化学镀方法制造布线基板的方法，该方法使不使用电镀抗蚀剂的金属沉淀。 该方法包括以下步骤：（a）在衬底上提供具有预定图案的催化剂层; （b）将基板浸渍在化学镀溶液中，从而使金属沉淀在催化剂层上以提供第一金属层; （c）将基板的顶表面暴露于蒸汽; 和（d）将基板浸入化学镀溶液中，从而在第一金属层上沉淀金属，以提供第二金属层。

公开(公告)号：US5869126A

公开(公告)日：1999-02-09

申请号：US870998

申请日：1997-06-06

Applicant: Peter Kukanskis

Inventor： Peter Kukanskis

IPC: H05K3/18 ,  H05K3/24 ,  H05K3/28 ,  H05K3/42 ,  B05D5/12

CPC classification number: H05K3/428 ,  H05K3/243 ,  H05K2203/0565 ,  H05K2203/0571 ,  H05K2203/072 ,  H05K3/28 ,  H05K3/282 ,  Y10T29/49165

Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates a novel processing sequence for this manufacturing process which method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce the circuit boards.

公开(公告)号：US4388351A

公开(公告)日：1983-06-14

申请号：US330993

申请日：1981-12-15

Applicant: Ernest W. Sawyer

Inventor： Ernest W. Sawyer

IPC: C23C18/16 ,  H05K3/18 ,  B05D3/04

CPC classification number: C23C18/1605 ,  H05K3/184 ,  H05K2203/0565 ,  H05K2203/0783 ,  H05K2203/0789

Abstract: A printed circuit board is formed by forming a negative resist pattern over the surface of a substrate, etching the surface, sensitizing and catalyzing the surface, stripping the negative mask and catalytic layer thereover leaving a positive catalytic circuit pattern on the substrate and electrolessly plating copper over the catalytic image. A preferred variation of this method includes flash plating a thin porous electroless deposit over the catalyzed substrate prior to stripping the resist layer.

Abstract translation: 通过在基板的表面上形成负的抗蚀剂图案，蚀刻表面，使表面感光和催化，形成印刷电路板，剥离负极掩模和催化剂层，从而在基板上留下积极的催化电路图案，并且无电镀铜 超过催化图像。 该方法的优选变型包括在剥离抗蚀剂层之前在催化底物上闪镀薄的多孔无电沉积物。

公开(公告)号：US3554780A

公开(公告)日：1971-01-12

申请号：US3554780D

申请日：1967-08-28

Applicant: ROHM & HAAS

Inventor： MILLER VERNON F ,  GEHMAN DAVID R

IPC: C23C18/16 ,  C25D5/02 ,  H05K3/18 ,  B44D1/52

CPC classification number: C25D5/022 ,  C23C18/1605 ,  H05K3/184 ,  H05K2203/0565 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/0789

Abstract: THIS INVENTION RELATES TO AN IMPROVEMENT IN T HE METALLIZING OF VARIOUS SURFACES WHEREIN AN ACID RESISTANT BUT ALKALINE REMOVABLE STOP-OFF COATING IS APPLIED TO SELECTED PORTIONS OF THE SURFACE OF AN ARTICLE TO BE PLATED FOR THE PURPOSE OF MASKING PARTICULAR AREAS WHICH ARE TO REMAIN UNPLATED DURING THE PLATING PROCESS. THE STOP-OFF COATING COMPOSITIONS ARE AQUEOUS DISPERSIONS OF VINYL EMULSION COPOLYMERS C ONTAINING AT LEAST ONE CARBXYLIC ACID. THE PROCESS OF THIS INVENTION IS PARTICULARLY APPLICABLE TO A SURFACE FORMED FROM A PLASTIC OR SYNTHETIC POLYMETRIC MATERIAL.