-
公开(公告)号：US09589920B2
公开(公告)日：2017-03-07
申请号：US14836111
申请日：2015-08-26
发明人： Dror Hurwitz , Alex Huang
IPC分类号： H01L23/31 , H01L23/00 , H01L23/29 , H01L23/498 , H01L21/78 , H01L21/027 , H01L21/683 , H01L23/495 , H01L23/14 , H01L21/56 , H01L23/13
CPC分类号： H01L24/16 , H01L21/0273 , H01L21/4846 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/13 , H01L23/142 , H01L23/291 , H01L23/293 , H01L23/3114 , H01L23/3135 , H01L23/3171 , H01L23/49548 , H01L23/49586 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49861 , H01L23/49866 , H01L23/5389 , H01L23/544 , H01L24/08 , H01L24/11 , H01L24/19 , H01L24/20 , H01L24/95 , H01L24/96 , H01L24/97 , H01L2221/68327 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2223/54486 , H01L2224/04105 , H01L2224/05124 , H01L2224/11002 , H01L2224/11462 , H01L2224/11614 , H01L2224/11622 , H01L2224/1182 , H01L2224/12105 , H01L2224/13013 , H01L2224/13014 , H01L2224/13016 , H01L2224/13022 , H01L2224/13023 , H01L2224/13147 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/05042 , H01L2924/07025 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/2064 , H01L2924/3511 , H01L2924/37001 , H01L2924/00012
摘要： An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.
摘要翻译： 一种嵌入式管芯封装和制造方法，所述管芯封装包括在钝化层中具有I / O接触焊盘的管芯，其中所述管芯接触焊盘通过粘合/阻挡层耦合到特征层的第一侧，以及层 支柱从特征层的第二侧延伸，模具，特征层和柱状层被电介质材料包封，并且其中特征层包括在光学引导下通过光致抗蚀剂的激光曝光单独拉制的布线 成像系统，用于与管芯的I / O接触焊盘两者良好的对准，并随后沉积相对于封装边缘定位的柱。
-
公开(公告)号：US20150294896A1
公开(公告)日：2015-10-15
申请号：US14249282
申请日：2014-04-09
发明人： Dror Hurwitz , Alex Huang
IPC分类号： H01L21/768 , H01L21/78 , H01L21/56 , H01L21/66
CPC分类号： H01L25/00 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/042 , H01L25/0652 , H01L25/071 , H01L25/072 , H01L25/0753 , H01L2224/04105 , H01L2924/181 , H01L2924/3511 , H01L2933/005 , H01L2924/00
摘要： A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from a through via at least partway over each chip; dicing the array to create separate dies comprising at least one embedded chip having a contract pad coupled to a through via adjacent the chip.
摘要翻译： 一种制造嵌入式管芯封装的方法，包括以下步骤：获得芯片插座的蜂窝阵列，使得每个芯片插座由具有第一聚合物的聚合物基体的框架和穿过框架围绕每个插座的至少一个通孔支架围绕; 将蜂窝状阵列放置在透明胶带上，使得蜂巢梳状阵列的下侧接触透明带; 将芯片端子放置在每个芯片插座中，使芯片的下侧与透明胶带接触; 使用通过胶带的光学成像将芯片与通孔柱对准; 将包装材料涂覆在蜂窝状阵列上的芯片周围，并固化填料以将芯片嵌入五面; 使包装材料变薄并平坦化，以暴露阵列上侧通孔的上端; 去除透明胶带; 在蜂窝阵列的下侧和芯片的下侧上施加导体的特征层，以将每个管芯的至少一个端子耦合到至少一个通孔; 在所述蜂窝状阵列的上侧上施加导体的特征层，使得至少一个导体至少在每个芯片的一半上从通孔延伸; 对所述阵列进行切割以形成分开的裸片，其包括至少一个嵌入式芯片，所述至少一个嵌入式芯片具有耦合到邻近所述芯片的通孔的合约焊盘。
-
公开(公告)号：US08816218B2
公开(公告)日：2014-08-26
申请号：US13482074
申请日：2012-05-29
申请人： Dror Hurwitz
发明人： Dror Hurwitz
CPC分类号： H05K1/11 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K3/46 , Y10T156/10 , H01L2924/00
摘要： A multilayer composite electronic structure comprising at least two feature layers extending in an X-Y plane and separated by a via layer comprising a dielectric material that is sandwiched between two adjacent feature layers, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, wherein a first via has different dimensions in the X-Y plane from a second via in the via layer.
摘要翻译： 一种多层复合电子结构，包括至少两个特征层，所述特征层在XY平面中延伸并且由包含夹在两个相邻特征层之间的电介质材料的通孔层隔开，所述通孔层包括通孔，所述通孔在Z方向上连接相邻的特征层 垂直于XY平面，其中第一通孔在XY平面中具有与通孔层中的第二通孔不同的尺寸。
-
公开(公告)号：US10236854B2
公开(公告)日：2019-03-19
申请号：US15950886
申请日：2018-04-11
发明人： Dror Hurwitz , Alex Huang
摘要： A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist stripping away the photoresist and laminating.
-
公开(公告)号：US20170127527A1
公开(公告)日：2017-05-04
申请号：US15409221
申请日：2017-01-18
发明人： Dror Hurwitz , Alex Huang
CPC分类号： H05K3/007 , C25D5/022 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/18 , H01L2924/181 , H01L2924/3511 , H05K1/0313 , H05K1/115 , H05K3/0064 , H05K3/064 , H05K2201/032 , H05K2201/09609 , H05K2201/10242 , H01L2924/00
摘要： An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.
-
公开(公告)号：US09240392B2
公开(公告)日：2016-01-19
申请号：US14249282
申请日：2014-04-09
发明人： Dror Hurwitz , Alex Huang
IPC分类号： H01L25/00 , H01L25/075 , H01L25/07 , H01L25/065 , H01L25/04
CPC分类号： H01L25/00 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/042 , H01L25/0652 , H01L25/071 , H01L25/072 , H01L25/0753 , H01L2224/04105 , H01L2924/181 , H01L2924/3511 , H01L2933/005 , H01L2924/00
摘要： A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from a through via at least partway over each chip; dicing the array to create separate dies comprising at least one embedded chip having a contract pad coupled to a through via adjacent the chip.
摘要翻译： 一种制造嵌入式管芯封装的方法，包括以下步骤：获得芯片插座的蜂窝阵列，使得每个芯片插座由具有第一聚合物的聚合物基体的框架和穿过框架围绕每个插座的至少一个通孔支架围绕; 将蜂窝状阵列放置在透明胶带上，使得蜂巢梳状阵列的下侧接触透明带; 将芯片端子放置在每个芯片插座中，使芯片的下侧与透明胶带接触; 使用通过胶带的光学成像将芯片与通孔柱对准; 将包装材料涂覆在蜂窝状阵列上的芯片周围，并固化填料以将芯片嵌入五面; 使包装材料变薄并平坦化，以暴露阵列上侧通孔的上端; 去除透明胶带; 在蜂窝阵列的下侧和芯片的下侧上施加导体的特征层，以将每个管芯的至少一个端子耦合到至少一个通孔; 在所述蜂窝状阵列的上侧上施加导体的特征层，使得至少一个导体至少在每个芯片的一半上从通孔延伸; 对所述阵列进行切割以形成分开的裸片，其包括至少一个嵌入式芯片，所述至少一个嵌入式芯片具有耦合到邻近所述芯片的通孔的合约焊盘。
-
公开(公告)号：US20150296617A1
公开(公告)日：2015-10-15
申请号：US14269884
申请日：2014-05-05
发明人： Dror Hurwitz , Alex Huang
CPC分类号： H05K3/007 , C25D5/022 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/18 , H01L2924/181 , H01L2924/3511 , H05K1/0313 , H05K1/115 , H05K3/0064 , H05K3/064 , H05K2201/032 , H05K2201/09609 , H05K2201/10242 , H01L2924/00
摘要： An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.
摘要翻译： 由有机矩阵框架限定的芯片插座阵列，该有机矩阵框架通过有机矩阵框架围绕插座，并且还包括通过有机矩阵框架的金属通孔网格。 在一个实施例中，面板包括芯片插座阵列，每个芯片插座由包括通过有机矩阵框架的铜通孔网格的有机矩阵框架包围和限定。 面板包括具有插座的至少第一区域，该插座具有用于接收一种类型的芯片的一组尺寸，以及具有插座的第二区域和用于接收第二类型芯片的另一组尺寸。
-
公开(公告)号：US20140377914A1
公开(公告)日：2014-12-25
申请号：US14485948
申请日：2014-09-15
发明人： Dror Hurwitz , Shih-Fu Alex Huang
CPC分类号： H01L24/92 , H01L21/4825 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/563 , H01L21/566 , H01L21/6835 , H01L23/145 , H01L23/4952 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2221/68318 , H01L2221/68331 , H01L2221/68345 , H01L2221/68381 , H01L2221/68386 , H01L2224/16225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/85 , H01L2224/92147 , H01L2924/12042 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.
-
9.发明申请Multilayer Electronic Structures with Improved Control of Dielectric Thickness 有权具有改善电介质厚度控制的多层电子结构公开(公告)号：US20140102765A1
公开(公告)日：2014-04-17
申请号：US13652122
申请日：2012-10-15
发明人： Dror Hurwitz , Alex Huang
CPC分类号： H05K1/0298 , H05K3/0061 , H05K3/4647 , H05K2201/10378 , Y10T29/49126 , Y10T29/49158 , Y10T29/49163
摘要： A method of fabricating a multilayer electronic support structure comprising electroplating copper substructures, laying a dielectric pre-preg comprising a polymer resin over the copper substructures, and pressing to pressures of 200 to 600 PSI against a release film having a higher hardness than the resin of the prepreg but a lower hardness than the cured resin, and heating through a curing cycle whilst maintaining pressure.
摘要翻译： 一种制造多层电子支撑结构的方法，包括电镀铜底层结构，将包含聚合物树脂的电介质预浸料铺设在铜基底结构上，并压制200至600PSI的压力，以抵抗具有比 预浸料，但硬度低于固化树脂，并且通过固化循环加热同时保持压力。
-
公开(公告)号：US10014843B2
公开(公告)日：2018-07-03
申请号：US13962316
申请日：2013-08-08
发明人： Dror Hurwitz , Alex Huang
CPC分类号： H03H7/0138 , H01L27/016 , H01L28/10 , H01L28/60 , H03H3/00 , H03H7/0115 , H03H2001/0085
摘要： A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter;the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.033 秒)
