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公开(公告)号：US20240179851A1
公开(公告)日：2024-05-30
申请号：US18550145
申请日：2022-03-11
Applicant: Atotech Deutschland GmbH & Co. KG
Inventor： Valentina BELOVA-MAGRI , Stefanie ACKERMANN , Fabian MICHALIK , Philipp HAARMANN , Martin THOMS , Norbert LÜTZOW , Jan KNAUP , Tatjana KÖNIGSMANN
CPC classification number: H05K3/389 , H05K3/0064 , H05K3/227 , H05K3/26 , H05K3/385 , H05K2203/0315 , H05K2203/0766
Abstract: The present invention relates to a method for increasing adhesion strength between a surface of a copper, a copper alloy or a copper oxide and a surface of an organic material.
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公开(公告)号：US20230300988A1
公开(公告)日：2023-09-21
申请号：US18014831
申请日：2021-06-30
Applicant: Dätwyler Schweiz AG
Inventor： Ronny VRIJENS , Matthias SODDEMANN , Daniel Joel GLOOR
CPC classification number: H05K3/0064 , H05K1/0277 , H05K1/0393 , H05K3/12 , H05K2201/0133 , H05K2201/0129
Abstract: A method for producing an elastomeric component, preferably an elastomeric sealing component, including an elastomer body and a printed structure, preferably a printed electronic structure or circuit, on a surface of the elastomer body. The method includes: a. providing a planar foil of thermoplastic material having a printable surface; b. printing a structure onto the printable surface to obtain the printed structure; c. providing an elastomer substrate for forming the elastomer body; d. placing the planar foil with the printed structure onto the elastomer substrate; and e. laminating the combined planar foil and elastomer substrate by applying heat and pressure. The elastomeric component is obtained in that the elastomer substrate is formed to the shape of the elastomer body before step d); the elastomer substrate is formed to the shape of the elastomer body during lamination; or the elastomer substrate is formed to the shape of the elastomer body after lamination.
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公开(公告)号：US09974188B2
公开(公告)日：2018-05-15
申请号：US15090703
申请日：2016-04-05
Applicant: Compass Technology Company Limited
Inventor： Kelvin Po Leung Pun , Chee Wah Cheung
CPC classification number: H05K3/0041 , G06F3/041 , H05K1/0278 , H05K1/0306 , H05K1/0326 , H05K1/0346 , H05K1/09 , H05K1/144 , H05K3/0064 , H05K3/025 , H05K3/027 , H05K3/381 , H05K2201/0141 , H05K2201/0145 , H05K2201/0154 , H05K2201/0323 , H05K2201/042 , H05K2203/0152 , H05K2203/0376 , H05K2203/095 , H05K2203/1545
Abstract: A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left therebetween.
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公开(公告)号：US09949373B2
公开(公告)日：2018-04-17
申请号：US15409221
申请日：2017-01-18
Inventor： Dror Hurwitz , Alex Huang
CPC classification number: H05K3/007 , C25D5/022 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/18 , H01L2924/181 , H01L2924/3511 , H05K1/0313 , H05K1/115 , H05K3/0064 , H05K3/064 , H05K2201/032 , H05K2201/09609 , H05K2201/10242 , H01L2924/00
Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.
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公开(公告)号：US09929484B1
公开(公告)日：2018-03-27
申请号：US15384811
申请日：2016-12-20
Applicant: General Electric Company
Inventor： Boban George
CPC classification number: A61B6/502 , H01L51/5237 , H05K1/02 , H05K1/11 , H05K3/0064 , H05K2201/09472 , H05K2203/063
Abstract: In the present invention, an electrical connector is formed with contacts on one side of a printed circuit board that are electrically coupled through the board in a known manner. A backing plate formed of a dielectric material is applied to the board over the contacts. The backing plate includes openings extending through the backing plate that are in alignment with the contacts in order to allow electrical connections to be made with the contacts, but while also isolating the contacts from the exterior surface of the backing layer. The backing layer is affixed to the board over the contacts by an adhesive resin layer having an aperture cut into the layer. The aperture cut into the layer surrounds the contacts on the board, and due to the low or no flow nature of the resin, does not flow onto the contacts to cover the contacts.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180027646A1
公开(公告)日：2018-01-25
申请号：US15542783
申请日：2015-12-28
Applicant: AutoNetworks Technologies, Ltd. , Sumitomo Wiring Systems, Ltd. , SUMITOMO ELECTRIC INDUSTRIES, LTD.
Inventor： Tatsuya Sumida
CPC classification number: H05K1/0204 , H05K1/0209 , H05K3/0064 , H05K3/10 , H05K3/202 , H05K3/4007 , H05K7/1432 , H05K7/20854 , H05K7/209 , H05K2201/0382 , H05K2201/062 , H05K2201/066 , H05K2201/10272 , H05K2201/10409
Abstract: A circuit assembly includes a circuit board having an insulating board in which a conductive path is formed on an insulating plate and a plurality of busbars that are bonded to one side of the insulating board, an insulating layer that is printed to the plurality of busbars so as to couple adjacent ones of the plurality of busbars to each other, a heat dissipation member on which the insulating layer is placed and which is configured to dissipate heat conducted from the insulating layer, a fixing member that is configured to fix the circuit board and the heat dissipation member to each other in a state in which the insulating layer is sandwiched between the heat dissipation member and the plurality of busbars.
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公开(公告)号：US20170374741A1
公开(公告)日：2017-12-28
申请号：US15700433
申请日：2017-09-11
Inventor： Jonathan Douglas Hatch , Stephen McGarry Hatch
CPC classification number: H05K1/0306 , H05K1/02 , H05K1/028 , H05K1/0393 , H05K1/115 , H05K1/144 , H05K3/0023 , H05K3/0064 , H05K3/007 , H05K3/048 , H05K3/103 , H05K3/125 , H05K3/386 , H05K3/389 , H05K3/4611 , H05K3/4644 , H05K2201/0145 , H05K2201/0154 , H05K2201/05 , H05K2201/09009 , H05K2203/0152
Abstract: A PCB page blank includes a flexible substrate, a curable adhesive, a conductive layer, and a conductive layer support. The flexible substrate receives an opaque negative circuit pattern thereon. Portions of the curable adhesive not obscured by the circuit pattern may bond to portions of the conductive layer when exposed to light. The bonded portions of the conductive layer shear or tear from non-bonded portions of the conductive layer such that the bonded portions remain with the flexible substrate and the non-bonded portions remain with the conductive layer support when the flexible substrate and the conductive layer support are separated. The flexible substrate and the bonded portions of the conductive layer thus form a PCB prototype with the bonded portions of the conductive layer forming circuit traces of the circuit pattern.
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公开(公告)号：US09832869B2
公开(公告)日：2017-11-28
申请号：US14910093
申请日：2014-07-09
Applicant: DSM IP ASSETS B.V.
IPC: H05K1/00 , H05K3/00 , C08G69/26 , H05K1/03 , B29C55/00 , B29C55/12 , C08J5/18 , C08L77/06 , B29C55/04 , H05K1/02 , B29K77/00
CPC classification number: H05K1/0346 , B29C55/005 , B29C55/04 , B29C55/12 , B29K2077/00 , C08G69/26 , C08G69/265 , C08J5/18 , C08J2377/06 , C08L77/06 , H05K1/028 , H05K1/0366 , H05K1/0373 , H05K1/0393 , H05K3/0064
Abstract: The invention relates to a stretched polymer film made of a polyamide composition comprising a semi-crystalline semi-aromatic polyamide (PPA), wherein the PPA consists of repeat units derived from aromatic dicarboxylic acid comprising at least 80 mole % of terephthalic acid, relative to the total amount of aromatic dicarboxylic acid; and diamine comprising at least 5 mole % 1,4-butanediamine and at least 5 mole % 1,6-hexanediamine, relative to the total amount of diamine, the combined amount of 1,4-butanediamine and 1,6-hexanediamine being at least 60 mole % relative to the total amount of diamine; and 0-2 mole % of other monomeric units, relative to the total amount of aromatic dicarboxylic acid, diamine and other monomeric units. The invention further relates to a process for preparing the polyamide film by melt extrusion and stretching of the film.
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公开(公告)号：US09767241B2
公开(公告)日：2017-09-19
申请号：US12749254
申请日：2010-03-29
Applicant: Norman L. Rogers , John W. Hoffman , Jun Feng , Charles Krauter
Inventor： Norman L. Rogers , John W. Hoffman , Jun Feng , Charles Krauter
CPC classification number: G06F17/5068 , H05K1/0206 , H05K1/029 , H05K1/0295 , H05K1/111 , H05K1/114 , H05K3/0005 , H05K3/0064 , H05K2201/093 , H05K2201/09309 , H05K2201/09418 , H05K2201/09454 , H05K2201/09663 , H05K2201/09954 , H05K2201/10022 , H05K2201/10166 , H05K2201/10636 , H05K2203/173 , Y02P70/611 , Y10T29/49117 , Y10T29/49124
Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.
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10.发明授权Conductive film substrate, transparent conductive film, and method for producing transparent conductive film 有权导电膜基板，透明导电膜，以及透明导电膜的制造方法公开(公告)号：US09549462B2
公开(公告)日：2017-01-17
申请号：US14780529
申请日：2014-03-03
Applicant: KANEKA CORPORATION
Inventor： Tooru Irie , Takahisa Fujimoto , Takashi Kuchiyama , Hironori Hayakawa , Shinya Omoto , Kenji Yamamoto
CPC classification number: H05K1/0274 , G06F3/044 , G06F2203/04103 , G06F2203/04112 , H05K1/0296 , H05K1/0326 , H05K1/09 , H05K3/0064 , H05K3/06 , H05K3/067 , H05K3/108 , H05K3/227 , H05K3/388 , H05K2201/0108 , H05K2201/0145 , H05K2201/0317 , H05K2201/09663 , H05K2201/0979
Abstract: Provided is a transparent conductive film including a transparent electrode layer composed of a patterned thin metal wire on at least one surface of a transparent film substrate. The line width of the wire is 5 μm or less. The wire includes a first metal layer and a second metal layer that is in contact with the first metal layer, in this order from a transparent film substrate side. Both of the first and second metal layers contain copper in an amount of 90% by weight or more. The total film thickness of the first and second metal layers is 150 to 1000 nm. The diffraction angle 2θ of the (111) plane of the second metal layer is less than 43.400° as measured using a CuKα ray as an X-ray source, and the first metal layer has crystal properties different from those of the second metal layer.
Abstract translation: 提供一种透明导电膜，其包括在透明膜基板的至少一个表面上由图案化的金属细线构成的透明电极层。 线的线宽为5μm以下。 导线包括从透明膜基板一侧依次与第一金属层接触的第一金属层和第二金属层。 第一和第二金属层都含有90重量％以上的铜。 第一和第二金属层的总膜厚度为150〜1000nm。 使用CuKα射线作为X射线源测定的第二金属层的（111）面的衍射角2θ小于43.400°，第一金属层的结晶特性与第二金属层的晶体性质不同。
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