公开(公告)号：US20240341034A1

公开(公告)日：2024-10-10

申请号：US18623091

申请日：2024-04-01

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Susumu KAGOHASHI

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0242 ,  H05K1/09 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/423 ,  H05K1/0306 ,  H05K1/0373 ,  H05K2201/0209 ,  H05K2201/0338 ,  H05K2201/096 ,  H05K2203/0723

Abstract: A wiring substrate includes a core substrate having a through-hole conductor, a resin insulating layer formed on the core substrate, a conductor layer formed on the insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor formed in the insulating layer. The via conductor electrically connects the through-hole conductor and conductor layer. The via conductor includes the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a glass substrate and has a through hole penetrating through the glass substrate. The through-hole conductor is formed in the through hole. The seed layer is covering inner wall surface of the insulating layer in opening in which the via conductor is formed. The seed layer has a first portion and a second portion electrically connected to the first portion. That part of the first portion is formed on the second portion.

公开(公告)号：US11917756B2

公开(公告)日：2024-02-27

申请号：US17485672

申请日：2021-09-27

Applicant: IBIDEN CO., LTD.

Inventor： Yuji Ikawa

IPC: H05K3/00 ,  H05K1/09 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/09 ,  H05K3/0041 ,  H05K3/062 ,  H05K3/4632 ,  H05K3/0079

Abstract: A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.

公开(公告)号：US11849543B2

公开(公告)日：2023-12-19

申请号：US17084618

申请日：2020-10-29

Applicant: HZO, Inc.

Inventor： Sean Clancy ,  Benjamin Lawrence ,  Alexander Niebroski

IPC: H05K3/00 ,  H05K3/22 ,  H01J37/32 ,  G03F7/038 ,  G03F7/039

CPC classification number: H05K3/0041 ,  G03F7/038 ,  G03F7/039 ,  H01J37/3244 ,  H01J37/32963 ,  H05K3/0023 ,  H05K3/22 ,  H05K2203/095

Abstract: A plasma ashing system includes a plasma generator configured to generate a plasma from a gas source. The system further includes a plasma reaction chamber configured to house a substrate comprising a Parylene coating, wherein the plasma reaction chamber is configured to expose surfaces of the Parylene coating on the substrate to the plasma, wherein the plasma is configured to remove portions of the Parylene coating on the substrate.

公开(公告)号：US20190124778A1

公开(公告)日：2019-04-25

申请号：US15836937

申请日：2017-12-11

Applicant: Unimicron Technology Corp.

Inventor： Po-Hsuan LIAO ,  Wen-Fang LIU

IPC: H05K3/38 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K3/386 ,  H05K1/036 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0522 ,  H05K2203/1453

Abstract: A circuit board includes a substrate, a first dielectric layer, an adhesive layer, a second dielectric layer, and a conductive line. The first dielectric layer is disposed on the substrate. The adhesive layer is bonded to the first dielectric layer and has at least one through hole. The through hole has an inner wall. The second dielectric layer is disposed on the adhesive layer and has a second through hole communicated with the first through hole. The conductive line is located in the second through hole of the second dielectric layer and is in contact with the inner wall of the adhesive layer.

公开(公告)号：US20190124775A1

公开(公告)日：2019-04-25

申请号：US15836941

申请日：2017-12-11

Applicant: Unimicron Technology Corp.

Inventor： Po-Hsuan LIAO

IPC: H05K3/10 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/107 ,  H05K1/0219 ,  H05K1/0284 ,  H05K1/0298 ,  H05K1/11 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/06

Abstract: A circuit board includes a substrate, a first dielectric layer, an adhesive layer, a second dielectric layer, and a first conductive line. The first dielectric layer is disposed on the substrate. The adhesive layer is bonded to the first dielectric layer and has a top surface opposite to the substrate. The second dielectric layer is disposed on the adhesive layer and has at least one first through hole. The first conductive line is located in the first through hole of the second dielectric layer and is in contact with the top surface of the adhesive layer.

公开(公告)号：US09927349B2

公开(公告)日：2018-03-27

申请号：US15379319

申请日：2016-12-14

Applicant: CANON KABUSHIKI KAISHA

Inventor： Shinan Wang ,  Yutaka Setomoto

IPC: G01N21/00 ,  G01N21/17 ,  B06B1/02 ,  B06B1/06 ,  G01H9/00 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  G01N29/24 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42

CPC classification number: G01N21/1702 ,  B06B1/0292 ,  B06B1/06 ,  B06B1/0622 ,  G01H9/004 ,  G01N29/24 ,  G01N29/2406 ,  G01N29/2418 ,  G01N29/2437 ,  G01N2021/1706 ,  H01L21/76898 ,  H01L23/49827 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/06 ,  H05K3/4084 ,  H05K3/42 ,  H05K2201/09854 ,  H05K2203/025

Abstract: In a method of producing a device in which an element structure is provided on a substrate including a through wiring, a through hole is formed so as to extend from a first surface of the substrate to a second surface of the substrate disposed on an opposite side of the substrate to the first surface, the through wiring is formed by filling the through hole with an electrically conductive material, and the element structure is formed on a first surface side. In the step of forming the through hole, a degree of surface irregularities of an inner wall of the through hole is larger on the first surface side than on a second surface side.

公开(公告)号：US20170374747A1

公开(公告)日：2017-12-28

申请号：US15622733

申请日：2017-06-14

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K3/40 ,  H01L23/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/26 ,  H05K3/10 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81805 ,  H01L2924/00011 ,  H01L2924/01322 ,  H05K1/112 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/26 ,  H05K3/3473 ,  H05K3/4647 ,  H05K2201/09436 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/043 ,  H05K2203/0465 ,  H01L2924/00014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

公开(公告)号：US09820386B2

公开(公告)日：2017-11-14

申请号：US15074064

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Rahul Jain ,  Robert Alan May ,  Sheng Li ,  Sri Ranga Sai Boyapati

IPC: H05K3/00 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/0041 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/3452 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  H05K2203/0588 ,  H05K2203/095

Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

公开(公告)号：US20170280566A1

公开(公告)日：2017-09-28

申请号：US15619525

申请日：2017-06-11

Applicant: Southeast University

Inventor： Jintang SHANG ,  Mengying MA

IPC: H05K3/00 ,  H05K1/03 ,  H05K3/30 ,  H05K3/10

CPC classification number: H05K3/002 ,  H01L21/38 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01P3/003 ,  H01P5/02 ,  H03H2001/0021 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0029 ,  H05K3/0041 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/188 ,  H05K3/301 ,  H05K2203/1105

Abstract: A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly doped silicon wafer is dry etched to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays; a glass wafer is anodically bonded to the highly doped silicon mould wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly doped silicon passives; the passive component structure mould embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mould has been etched is filled with copper by electroplating; the highly doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.