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    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    1.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20110003433A1

    公开(公告)日：2011-01-06

    申请号：US12819379

    申请日：2010-06-21

    申请人： Yoichi HARAYAMA ,  Takaharu Yamano

    发明人： Yoichi HARAYAMA ,  Takaharu Yamano

    IPC分类号： H01L21/50

    CPC分类号： H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02333 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/11

    摘要： A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices.

    摘要翻译： 所公开的装置包括半导体器件的制造方法，其包括制备半导体衬底形成区域，围绕这些区域的划线区域以及形成在划线区域中并且比划线区域窄的切割区域的半导体衬底，形成校验图案和半导体芯片，形成 抗蚀剂膜，通过比划线区域窄的槽形成，并且比检查图案和切割区域宽，通过使用抗蚀剂膜的湿吹工艺去除检查图案，并在保护膜和半导体基板的部分共同形成槽 形成布线形成面，通过除去直到连接面露出，形成布线图案，切割半导体基板，绝缘层，绝缘层 树脂层和焊料 抗蚀剂层分离成单独的半导体器件。

    Manufacturing method of preparing a substrate with forming and removing the check patterns in scribing regions before dicing to form semiconductor device
    3.
    发明授权
    Manufacturing method of preparing a substrate with forming and removing the check patterns in scribing regions before dicing to form semiconductor device 有权
    在切割之前形成和去除划线区域中的检查图案以制备半导体器件的制备方法

    公开(公告)号：US08129259B2

    公开(公告)日：2012-03-06

    申请号：US12819379

    申请日：2010-06-21

    申请人： Yoichi Harayama ,  Takaharu Yamano

    发明人： Yoichi Harayama ,  Takaharu Yamano

    IPC分类号： H01L21/00

    CPC分类号： H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02333 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/11

    摘要： A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices.

    摘要翻译： 所公开的装置包括半导体器件的制造方法，其包括制备半导体衬底形成区域，围绕这些区域的划线区域以及形成在划线区域中并且比划线区域窄的切割区域的半导体衬底，形成校验图案和半导体芯片，形成 抗蚀剂膜，通过比划线区域窄的槽形成，并且比检查图案和切割区域宽，通过使用抗蚀剂膜的湿吹工艺去除检查图案，并在保护膜和半导体基板的部分共同形成槽 形成布线形成面，通过除去直到连接面露出，形成布线图案，切割半导体基板，绝缘层，绝缘层 树脂层和焊料 抗蚀剂层分离成单独的半导体器件。