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公开(公告)号：US20230178160A1
公开(公告)日：2023-06-08
申请号：US17871422
申请日：2022-07-22
发明人： Hongtao Liu , Lei Jin , Xiangnan Zhao , Ying Huang , Lei Guan , Yuanyuan Min
IPC分类号： G11C29/02 , G11C29/52 , G11C11/4074 , G11C11/408
CPC分类号： G11C29/022 , G11C29/52 , G11C11/4074 , G11C11/4085
摘要： Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.
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公开(公告)号：US20230162798A1
公开(公告)日：2023-05-25
申请号：US18090444
申请日：2022-12-28
发明人： Kaiwei Li , Jianquan Jia , Yuanyuan Min , Ying Cui , Yali Song , Hongtao Liu , Xinlei Jia , An Zhang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/28
摘要： A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.
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公开(公告)号：US11423995B2
公开(公告)日：2022-08-23
申请号：US17186456
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
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公开(公告)号：US20220215883A1
公开(公告)日：2022-07-07
申请号：US17186429
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Kaikai You
摘要： A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre- charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.
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公开(公告)号：US11710529B2
公开(公告)日：2023-07-25
申请号：US17871472
申请日：2022-07-22
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
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公开(公告)号：US11670373B2
公开(公告)日：2023-06-06
申请号：US17186429
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Kaikai You
CPC分类号： G11C16/10 , G11C7/1048 , G11C16/0433 , G11C16/08 , G11C16/28 , G11C16/30 , G11C16/3404
摘要： A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.
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公开(公告)号：US20220215888A1
公开(公告)日：2022-07-07
申请号：US17186456
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
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公开(公告)号：US11864379B2
公开(公告)日：2024-01-02
申请号：US17568639
申请日：2022-01-04
发明人： Xuezhun Xie , Yali Song , Lei Jin , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia
CPC分类号： H10B41/27 , G11C5/025 , G11C16/0483 , G11C16/3436 , H10B43/27
摘要： The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.
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公开(公告)号：US20230326536A1
公开(公告)日：2023-10-12
申请号：US18203980
申请日：2023-05-31
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24
摘要： A three-dimensional (3D) memory device includes a first set of word lines coupled to first memory cells, a second set of word lines coupled to second memory cells, an interface dummy word line between the first and send sets of word lines, and a peripheral circuit coupled to the first and send memory cells. The peripheral circuit is configured to apply a first voltage to the interface dummy word line in a first pre-charge period when programming a first selected memory cell in the first memory cells, and apply a second voltage lower than the first voltage to the interface dummy word line in a second pre-charge period when programming a second selected memory cell in the second memory cells. Programing the first selected memory cell is earlier than the second selected memory cell.
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公开(公告)号：US20220359022A1
公开(公告)日：2022-11-10
申请号：US17871472
申请日：2022-07-22
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
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