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公开(公告)号：US10957409B1
公开(公告)日：2021-03-23
申请号：US16792304
申请日：2020-02-17
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.
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公开(公告)号：US20230162798A1
公开(公告)日：2023-05-25
申请号：US18090444
申请日：2022-12-28
发明人： Kaiwei Li , Jianquan Jia , Yuanyuan Min , Ying Cui , Yali Song , Hongtao Liu , Xinlei Jia , An Zhang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/28
摘要： A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.
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公开(公告)号：US20240312536A1
公开(公告)日：2024-09-19
申请号：US18354393
申请日：2023-07-18
发明人： Jiayin Han , Xinlei Jia , Kaikai You , An Zhang , Lei Jin
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2216/28
摘要： Examples of the present disclosure provide a memory and an operation method thereof, a memory system and an electronic device. The operation method comprises: applying a pass voltage to word lines coupled to unselected memory cells of one of memory strings according to a program order of a selected memory cell of the memory string when performing a read operation on the selected memory cell, wherein the earlier the program order of the selected memory cell is, the greater the pass voltage applied to the word lines coupled to the unselected memory cells of the memory string during the read operation is. In the examples of the present disclosure, the pass voltage applied to the word lines coupled to the unselected memory cells is determined according to the program order of the selected memory cell, i.e., according to different degrees of impact of a background pattern dependency effect experienced by the selected memory cell, such that the impact of the background pattern dependency effect can be decreased, and the read disturb is reduced.
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公开(公告)号：US20210174885A1
公开(公告)日：2021-06-10
申请号：US17180689
申请日：2021-02-19
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines. The memory device further includes a word line driver coupled to the control circuit and the word lines and configured to, in response to the control signal, apply a positive first voltage signal to each of the word lines that are coupled to the gate terminals of the top memory cells during a first time period in a pre-charge phase prior to a programming phase.
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公开(公告)号：US20220359021A1
公开(公告)日：2022-11-10
申请号：US17869511
申请日：2022-07-20
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.
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公开(公告)号：US10885990B1
公开(公告)日：2021-01-05
申请号：US16726947
申请日：2019-12-26
发明人： Xinlei Jia , Shan Li , Kaiwei Li , Jianquan Jia , Lei Jin , Kaikai You , Ying Cui , Yali Song , Wei Hou , Zhiyu Wang , Hongtao Liu
摘要： A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.
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