公开(公告)号：US08299631B2

公开(公告)日：2012-10-30

申请号：US13061456

申请日：2009-06-11

申请人： Takeshi Horiguchi ,  Takashi Matsui ,  Motoji Shiota

发明人： Takeshi Horiguchi ,  Takashi Matsui ,  Motoji Shiota

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H05K1/111 ,  G02F1/1345 ,  G02F1/13452 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/14152 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/29075

摘要： Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.

摘要翻译： 提供了抑制布线可靠性降低的半导体元件。 驱动器IC（10）具有沿着长边（11a和11b）沿方向（方向A）排列的多个输出凸块（12）。 输出凸块包括设置在长边的中心部附近的多个源极凸块（12a）和朝向长边的端部排列的多个栅极凸块（12b）。 源极凸块靠近长边（11a）布置，并且栅极凸块比源极凸点更靠近长边（11b）布置。

公开(公告)号：US20120080789A1

公开(公告)日：2012-04-05

申请号：US13377780

申请日：2010-02-02

申请人： Motoji Shiota ,  Hiroki Nakahama ,  Takashi Matsui ,  Takeshi Horiguchi

发明人： Motoji Shiota ,  Hiroki Nakahama ,  Takashi Matsui ,  Takeshi Horiguchi

IPC分类号： H01L23/498

CPC分类号： H01L24/14 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13013 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14151 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/26145 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/13099 ,  H01L2224/81 ,  H01L2224/83

摘要： Provided is a semiconductor chip having a narrowed pitch between terminals, the chip being capable of suppressing occurrence of poor connection between the chip and a substrate on which the chip is mounted. In an LSI chip including an input bump group, which is composed of a plurality of input bumps aligned in a line along one long side of its bottom surface, and an output bump group, which is composed of a plurality of output bumps arranged in a staggered manner along the other long side of the bottom surface, a dummy bump group is provided in an area between an area where the input bump group is provided and an area where the output bump group is provided, the dummy bump group including a plurality of rectangular dummy bumps which have long side extending along a direction perpendicular to the long sides of the bottom surface.

摘要翻译： 提供了一种在端子之间具有窄间距的半导体芯片，该芯片能够抑制芯片与其上安装芯片的基板之间的连接不良的发生。 在包括输入凸块组的LSI芯片中，所述输入凸块组由沿其底面的一个长边排列的多个输入凸块和输出凸块组组成，所述输出凸块组由多个输出凸块组成， 沿着底面的另一长边交错排列，在设置有输入凸块组的区域和设置有输出凸块组的区域之间的区域中设置有虚设凸块组，该虚设凸块组包括多个 具有沿着与底面的长边垂直的方向延伸的长边的矩形伪凸块。

公开(公告)号：US20120236230A1

公开(公告)日：2012-09-20

申请号：US13510721

申请日：2010-09-15

申请人： Hiroki Nakahama ,  Takashi Matsui ,  Takeshi Horiguchi ,  Motoji Shiota

发明人： Hiroki Nakahama ,  Takashi Matsui ,  Takeshi Horiguchi ,  Motoji Shiota

IPC分类号： G02F1/1335 ,  H01J9/00 ,  H05K13/04 ,  H05K1/18

CPC分类号： G02F1/1345 ,  G02F2001/13456 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02185 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13019 ,  H01L2224/16 ,  H01L2224/16013 ,  H01L2224/16112 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17107 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81424 ,  H01L2224/81481 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15788 ,  Y10T156/10 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.

摘要翻译： 公开了一种器件基板，其中在其表面上形成有端子（24）的绝缘层（60）形成在除了显示部分之外的玻璃基板（20）的整个表面上，因此，边界（外围 绝缘层（60）不接近设置有NCF（81）的区域，即靠近LSI芯片（40）的区域。 这防止绝缘层（60）被NCF（81）从其边界剥离，从而防止端子（24）断裂。 此外，端子（24）和突起电极（40a）通过绝缘层（60）的弹性而彼此永久地压接，并且可以确保其间的稳定的电连接。

公开(公告)号：US20110193239A1

公开(公告)日：2011-08-11

申请号：US13061456

申请日：2009-06-11

申请人： Takeshi Horiguchi ,  Takashi Matsui ,  Motoji Shiota

发明人： Takeshi Horiguchi ,  Takashi Matsui ,  Motoji Shiota

IPC分类号： H01L23/48

CPC分类号： H05K1/111 ,  G02F1/1345 ,  G02F1/13452 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/14152 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/29075

摘要： Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.

摘要翻译： 提供了抑制布线可靠性降低的半导体元件。 驱动器IC（10）具有沿着长边（11a和11b）沿方向（方向A）排列的多个输出凸块（12）。 输出凸块包括设置在长边的中心部附近的多个源极凸块（12a）和朝向长边的端部排列的多个栅极凸块（12b）。 源极凸块靠近长边（11a）布置，并且栅极凸块比源极凸点更靠近长边（11b）布置。

公开(公告)号：US20130335940A1

公开(公告)日：2013-12-19

申请号：US14002346

申请日：2012-03-01

申请人： Takashi Matsui ,  Motoji Shiota ,  Hiroki Nakahama

发明人： Takashi Matsui ,  Motoji Shiota ,  Hiroki Nakahama

IPC分类号： H05K1/18

CPC分类号： H05K1/18 ,  G02F1/13454 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10165 ,  H01L2224/13013 ,  H01L2224/13144 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81903 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/07802 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/111 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09745 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A wiring substrate (11) includes: a substrate; and, formed upon the substrate, a plurality of wiring lines, a plurality of circuit elements, and a plurality of connecting terminals (51) connected via the plurality of wiring lines. Each of the plurality of connecting terminals (51) includes a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) that is disposed in the depression part (60) and that at least partially covers each protrusion of the pair of protrusion parts (50).

摘要翻译： 布线基板（11）包括：基板; 并且在所述基板上形成有多条布线，多个电路元件以及经由所述多根布线连接的多个连接端子（51）。 多个连接端子（51）中的每一个包括在一对突出部（50）之间形成有凹部（60）的一对突出部（50），设置在该凹部 部分（60）并且至少部分地覆盖所述一对突出部分（50）中的每个突起。

公开(公告)号：US09207477B2

公开(公告)日：2015-12-08

申请号：US14113886

申请日：2012-04-23

申请人： Hiroki Miyazaki ,  Motoji Shiota ,  Takatoshi Kira ,  Gen Nagaoka ,  Seiji Muraoka ,  Makoto Tamaki ,  Keiji Aota ,  Yukio Shimizu ,  Takashi Matsui ,  Hiroki Nakahama ,  Hiroki Makino ,  Minoru Horino

发明人： Hiroki Miyazaki ,  Motoji Shiota ,  Takatoshi Kira ,  Gen Nagaoka ,  Seiji Muraoka ,  Makoto Tamaki ,  Keiji Aota ,  Yukio Shimizu ,  Takashi Matsui ,  Hiroki Nakahama ,  Hiroki Makino ,  Minoru Horino

IPC分类号： G02F1/1333 ,  G02F1/1345 ,  F21V8/00

CPC分类号： G02F1/133308 ,  G02B6/0001 ,  G02F1/1333 ,  G02F1/13336 ,  G02F1/13452

摘要： A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.

摘要翻译： 本发明的显示模块1包括第一板3，第二板4，基膜5和电路构件2.第一板3和第二板4彼此接合在一起。 基膜5设置在第一基板3和第二基板4之间，并且从第一基板3的端部向外延伸。基膜5具有绝缘性，延伸部弯曲到 第一板3和第二板4.电路构件2形成在基膜5上。

公开(公告)号：US20110075088A1

公开(公告)日：2011-03-31

申请号：US12995578

申请日：2009-04-10

申请人： Takashi Matsui ,  Motoji Shiota

发明人： Takashi Matsui ,  Motoji Shiota

IPC分类号： G02F1/1345 ,  H01L23/52

CPC分类号： H05K1/111 ,  G02F1/13452 ,  H01L2224/05553 ,  H05K2201/09409 ,  H05K2201/09672 ,  H05K2201/10674 ,  Y02P70/611

摘要： A wiring board of the present invention has pads disposed in a plurality of rows including: first row pads each being connected to a respective one of the connection wires that is long in length; and second row pads (30b) each being connected to a respective one of the connection wires that is shorter in length than that of first connection wires (10a) connected to the first row pads, each of the first connection wires (10a) being provided not in a region between adjacent ones of the second row pads (30b) but in a lower layer region of the second row pads (30b), in such a manner that at least a first insulating layer (20a) is sandwiched between the second row pads (30b) and the first connection wires (10a), and 0.8≦W1/W2≦1, where W1 is a line width of the first connection wires (10a) in the lower layer region of the second row pads (30b), and W2 is a width of the second row pads (30b).

摘要翻译： 本发明的布线基板具有排列成多行的焊盘，包括：第一行焊盘，各自连接到长度相等的连接线; 和第二排焊盘（30b）分别连接到长度比连接到第一行焊盘的第一连接线（10a）短的连接线中的每个连接线，每个第一连接线（10a）被设置 不是在相邻的第二列焊盘（30b）之间的区域中，而是在第二行焊盘（30b）的下层区域中，使得至少第一绝缘层（20a）夹在第二行 焊盘（30b）和第一连接线（10a），以及0.8＆lt; W1; W1 / W2＆nlE; 1，其中W1是第二行焊盘（30b）的下层区域中的第一连接线（10a）的线宽， ，W2是第二排焊盘（30b）的宽度。

公开(公告)号：US20110199569A1

公开(公告)日：2011-08-18

申请号：US12673307

申请日：2008-07-17

申请人： Takashi Matsui ,  Motoji Shiota

发明人： Takashi Matsui ,  Motoji Shiota

IPC分类号： G02F1/1345 ,  H05K1/11 ,  H01L23/532

CPC分类号： H05K1/117 ,  G02F1/1345 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/4644 ,  H05K2201/09672 ,  H05K2201/09709 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); each of the first metal wires (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to have a widthwise center in a lower region below the corresponding second-row pad (30b); and each of the first metal wires (10a) has widthwise edges provided, in a plan view, beyond widthwise edges of a corresponding one of the second-row pads (30b) in a region in which the first metal wire (10a) overlaps with the corresponding second-row pad (30b).

摘要翻译： 本发明的布线基板（1）的布置方式为：排列成多行的焊盘（30）包括：与金属线（10）之间的第一金属线（10a）连接的第一排焊盘（30a） 和连接到金属线（10）中的第二金属线（10b）的第二排焊盘（30b），第一金属线（10a）比第二金属线（10b）长; 每个第一金属线（10a）形成为通过至少绝缘层与相应的第二排焊盘（30b）分离，并且在下面的区域中具有宽度方向的中心 相应的第二排垫（30b）; 并且所述第一金属线（10a）中的每一个具有宽度方向的边缘，所述横向边缘在所述第一金属线（10a）与所述第一金属线（10a）重叠的区域中在所述第二列焊盘（30b）中的相应一个的横向边缘 对应的第二排垫（30b）。

公开(公告)号：US20140092338A1

公开(公告)日：2014-04-03

申请号：US14113886

申请日：2012-04-23

申请人： Hiroki Miyazaki ,  Motoji Shiota ,  Takatoshi Kira ,  Gen Nagaoka ,  Seiji Muraoka ,  Makoto Tamaki ,  Keiji Aota ,  Yukio Shimizu ,  Takashi Matsui ,  Hiroki Nakahama ,  Hiroki Makino ,  Minoru Horino

发明人： Hiroki Miyazaki ,  Motoji Shiota ,  Takatoshi Kira ,  Gen Nagaoka ,  Seiji Muraoka ,  Makoto Tamaki ,  Keiji Aota ,  Yukio Shimizu ,  Takashi Matsui ,  Hiroki Nakahama ,  Hiroki Makino ,  Minoru Horino

IPC分类号： G02F1/1333 ,  F21V8/00

CPC分类号： G02F1/133308 ,  G02B6/0001 ,  G02F1/1333 ,  G02F1/13336 ,  G02F1/13452

摘要： A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.

摘要翻译： 本发明的显示模块1包括第一板3，第二板4，基膜5和电路构件2.第一板3和第二板4彼此接合在一起。 基膜5设置在第一基板3和第二基板4之间，并且从第一基板3的端部向外延伸。基膜5具有绝缘性，延伸部弯曲到 第一板3和第二板4.电路构件2形成在基膜5上。

公开(公告)号：US08310645B2

公开(公告)日：2012-11-13

申请号：US12995578

申请日：2009-04-10

申请人： Takashi Matsui ,  Motoji Shiota

发明人： Takashi Matsui ,  Motoji Shiota

IPC分类号： G02F1/1343 ,  G02F1/1345

CPC分类号： H05K1/111 ,  G02F1/13452 ,  H01L2224/05553 ,  H05K2201/09409 ,  H05K2201/09672 ,  H05K2201/10674 ,  Y02P70/611

摘要： A wiring board of the present invention has pads disposed in a plurality of rows including: first row pads each being connected to a respective one of the connection wires that is long in length; and second row pads (30b) each being connected to a respective one of the connection wires that is shorter in length than that of first connection wires (10a) connected to the first row pads, each of the first connection wires (10a) being provided not in a region between adjacent ones of the second row pads (30b) but in a lower layer region of the second row pads (30b), in such a manner that at least a first insulating layer (20a) is sandwiched between the second row pads (30b) and the first connection wires (10a), and 0.8≦W1/W2≦1, where W1 is a line width of the first connection wires (10a) in the lower layer region of the second row pads (30b), and W2 is a width of the second row pads (30b).

摘要翻译： 本发明的布线基板具有排列成多行的焊盘，包括：第一行焊盘，各自连接到长度相等的连接线; 和第二排焊盘（30b）分别连接到长度比连接到第一行焊盘的第一连接线（10a）短的连接线中的每个连接线，每个第一连接线（10a）被设置 不是在相邻的第二列焊盘（30b）之间的区域中，而是在第二行焊盘（30b）的下层区域中，使得至少第一绝缘层（20a）夹在第二行 焊盘（30b）和第一连接线（10a），以及0.8＆lt; W1; W1 / W2＆nlE; 1，其中W1是第二行焊盘（30b）的下层区域中的第一连接线（10a）的线宽， ，W2是第二排焊盘（30b）的宽度。