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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08699262B2

    公开(公告)日：2014-04-15

    申请号：US13270299

    申请日：2011-10-11

    申请人： Takao Watanabe ,  Satoru Hanzawa ,  Yoshitaka Sasago

    发明人： Takao Watanabe ,  Satoru Hanzawa ,  Yoshitaka Sasago

    IPC分类号： G11C11/24

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2481

    摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.

    摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20120087178A1

    公开(公告)日：2012-04-12

    申请号：US13270299

    申请日：2011-10-11

    申请人： Takao WATANABE ,  Satoru Hanzawa ,  Yoshitaka Sasago

    发明人： Takao WATANABE ,  Satoru Hanzawa ,  Yoshitaka Sasago

    IPC分类号： G11C11/24

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2481

    摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.

    摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08132063B2

    公开(公告)日：2012-03-06

    申请号：US13191442

    申请日：2011-07-26

    申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： G11C29/00

    CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

    摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

    摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08730717B2

    公开(公告)日：2014-05-20

    申请号：US13104005

    申请日：2011-05-09

    申请人： Satoru Hanzawa ,  Yoshitaka Sasago

    发明人： Satoru Hanzawa ,  Yoshitaka Sasago

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2454 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

    摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).

    摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储器件。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07996735B2

    公开(公告)日：2011-08-09

    申请号：US12469778

    申请日：2009-05-21

    申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

    IPC分类号： G11C29/00

    CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

    摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

    摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

    Semiconductor storage device and method for manufacturing same
    9.
    发明授权
    Semiconductor storage device and method for manufacturing same 有权
    半导体存储装置及其制造方法

    公开(公告)号：US08563961B2

    公开(公告)日：2013-10-22

    申请号：US13515435

    申请日：2010-12-13

    申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体 层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    10.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20120248399A1

    公开(公告)日：2012-10-04

    申请号：US13515435

    申请日：2010-12-13

    申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    IPC分类号： H01L27/24

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。