公开(公告)号：US11923353B2

公开(公告)日：2024-03-05

申请号：US17874492

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jen Lai ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Chen-Shien Chen ,  Kuo-Chio Liu

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/60 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/60 ,  H01L24/02 ,  H01L24/96 ,  H01L25/105 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16146 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

公开(公告)号：US10573573B2

公开(公告)日：2020-02-25

申请号：US15925790

申请日：2018-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L21/56 ,  H01L23/00 ,  H01L25/075

Abstract: A package includes a die, a plurality of first conductive structures, a plurality of second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns or conical frustums. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

公开(公告)号：US20190295913A1

公开(公告)日：2019-09-26

申请号：US15925790

申请日：2018-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A package includes a die, a plurality of first conductive structures, a plurality of second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns or conical frustums. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

公开(公告)号：US11864369B2

公开(公告)日：2024-01-02

申请号：US17691879

申请日：2022-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Hung-Yu Ye ,  Chung-Yi Lin ,  Yun-Ju Pan ,  Chee-Wee Liu

IPC: H01L27/11 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/324 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

公开(公告)号：US20210097228A1

公开(公告)日：2021-04-01

申请号：US16730406

申请日：2019-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chung Lin ,  Chung-Yi Lin ,  Yen-Sen Wang

IPC: G06F30/3953 ,  G06F30/398 ,  G03F1/36

Abstract: A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.

公开(公告)号：US20220399325A1

公开(公告)日：2022-12-15

申请号：US17874492

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jen Lai ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Chen-Shien Chen ,  Kuo-Chio Liu

IPC: H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L21/56 ,  H01L23/60 ,  H01L23/00

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

公开(公告)号：US11282843B2

公开(公告)日：2022-03-22

申请号：US16943916

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Hung-Yu Ye ,  Chung-Yi Lin ,  Yun-Ju Pan ,  Chee-Wee Liu

IPC: H01L21/324 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a first semiconductor fin, a second semiconductor fin, first source/drain features, second source/drain features, a first gate structure, a second gate structure, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first semiconductor fin and the second semiconductor fin are adjacent to each other. The first source/drain features are on opposite sides of the first semiconductor fin. The second source/drain features are on opposite sides of the second semiconductor fin. The first gate structure is over the first semiconductor fin. The second gate structure is over the second semiconductor fin. The first VGAA transistor is over one of the first source/drain features. The second VGAA transistor is over one of the second source/drain features.

公开(公告)号：US11036911B2

公开(公告)日：2021-06-15

申请号：US16730406

申请日：2019-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chung Lin ,  Chung-Yi Lin ,  Yen-Sen Wang

IPC: G06F30/3953 ,  G06F30/398 ,  G03F1/36 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528

Abstract: A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.