公开(公告)号：US20210366824A1

公开(公告)日：2021-11-25

申请号：US16881000

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Wei Chung ,  Yen-Sen Wang

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

摘要： A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.

公开(公告)号：US11036911B2

公开(公告)日：2021-06-15

申请号：US16730406

申请日：2019-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Chung Lin ,  Chung-Yi Lin ,  Yen-Sen Wang

IPC分类号： G06F30/3953 ,  G06F30/398 ,  G03F1/36 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528

摘要： A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.

公开(公告)号：US11929288B2

公开(公告)日：2024-03-12

申请号：US17991153

申请日：2022-11-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhe-Ching Lu ,  Bao-Ru Young ,  Yen-Sen Wang ,  Tsung-Chieh Tsai

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

公开(公告)号：US20210074656A1

公开(公告)日：2021-03-11

申请号：US17101567

申请日：2020-11-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Wei Chung ,  Yen-Sen Wang

IPC分类号： H01L23/00 ,  H01L21/768 ,  G06F30/394

摘要： A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

公开(公告)号：US20240213099A1

公开(公告)日：2024-06-27

申请号：US18601074

申请日：2024-03-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhe-Ching Lu ,  Yen-Sen Wang ,  Bao-Ru Young ,  Tsung-Chieh Tsai

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

公开(公告)号：US20210100103A1

公开(公告)日：2021-04-01

申请号：US16939676

申请日：2020-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Wei Chung ,  Yen-Sen Wang

IPC分类号： H05K1/16 ,  G06F30/392 ,  H01L49/02 ,  H05K1/11

摘要： An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.

公开(公告)号：US20210098310A1

公开(公告)日：2021-04-01

申请号：US16938401

申请日：2020-07-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhe-Ching Lu ,  Bao-Ru Young ,  Yen-Sen Wang ,  Tsung-Chieh Tsai

IPC分类号： H01L21/8238 ,  H01L27/092

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.

公开(公告)号：US20190005180A1

公开(公告)日：2019-01-03

申请号：US15637484

申请日：2017-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Cheng Yeh ,  Yen-Sen Wang ,  Ming-Yi Lin

IPC分类号： G06F17/50

摘要： Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.

公开(公告)号：US20240363561A1

公开(公告)日：2024-10-31

申请号：US18768621

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Wei Chung ,  Yen-Sen Wang

IPC分类号： H01L23/00 ,  G06F30/394 ,  H01L21/768

CPC分类号： H01L24/03 ,  G06F30/394 ,  H01L21/76865 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/03001 ,  H01L2224/0347 ,  H01L2924/3512

摘要： A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

公开(公告)号：US20230116270A1

公开(公告)日：2023-04-13

申请号：US18053220

申请日：2022-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Wei Chung ,  Yen-Sen Wang

IPC分类号： H01L23/00 ,  H01L21/768 ,  G06F30/394

摘要： A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.