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公开(公告)号:US12132094B2
公开(公告)日:2024-10-29
申请号:US17313428
申请日:2021-05-06
发明人: Te-An Chen , Meng-Han Lin
IPC分类号: H01L29/66 , H01L29/16 , H01L29/423
CPC分类号: H01L29/66545 , H01L29/16 , H01L29/4236 , H01L29/66484
摘要: A method for manufacturing a semiconductor device includes forming a first CPODE dummy poly gate and a second CPODE dummy poly gate on a semiconductor substrate; removing the first CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a first trench extending into the semiconductor substrate; filling the first trench with a first dielectric material to form a first isolation structure to isolate the first and second transistors from each other; removing the second CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a second trench extending into the semiconductor substrate; and filling the second trench with a second dielectric material having a dielectric composition different from that of the first dielectric material to form a second isolation structure to isolated the third and fourth transistors from each other.
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公开(公告)号:US11508816B2
公开(公告)日:2022-11-22
申请号:US17192607
申请日:2021-03-04
发明人: Te-An Chen , Meng-Han Lin
IPC分类号: H01L29/10 , H01L21/76 , H01L21/265 , H01L21/762 , H01L29/78
摘要: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate including a well region and an adjustment region over the well region. An isolation structure is disposed over the substrate and at least partially surrounds the well region and the adjustment region. An epitaxial layer is disposed over the adjustment region and surrounded by the isolation structure. A gate structure is disposed on the epitaxial layer. The present disclosure also provides a method for forming a semiconductor structure.
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公开(公告)号:US20220367451A1
公开(公告)日:2022-11-17
申请号:US17876536
申请日:2022-07-29
发明人: Meng-Han Lin , Te-An Chen
IPC分类号: H01L27/088 , H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/423
摘要: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.
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公开(公告)号:US11069714B1
公开(公告)日:2021-07-20
申请号:US16732230
申请日:2019-12-31
发明人: Meng-Han Lin , Te-An Chen
IPC分类号: H01L27/12 , H01L21/762 , H01L29/66 , H01L29/06 , H01L21/84
摘要: An integrated circuit includes a substrate having a first region and a second region, a first isolation structure disposed in the substrate and separating the first region from the second region, a first device disposed in the first region, a second device disposed in the second region, and a semiconductor dummy structure disposed on the first isolation structure. The first isolation structure has first top surface and a second top surface lower than the first top surface. The semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface and a boundary between the first top surface and the second top surface.
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公开(公告)号:US20240347579A1
公开(公告)日:2024-10-17
申请号:US18757744
申请日:2024-06-28
发明人: Meng-Han Lin , Te-Hsin Chiu , Wei Cheng Wu , Te-An Chen
IPC分类号: H01G4/30 , H01L21/8234 , H01L27/06 , H01L27/08
CPC分类号: H01L28/40 , H01L21/823481 , H01L27/0629 , H01L27/0805 , H01L27/0811
摘要: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.
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公开(公告)号:US12087809B2
公开(公告)日:2024-09-10
申请号:US18078418
申请日:2022-12-09
发明人: Meng-Han Lin , Te-Hsin Chiu , Wei Cheng Wu , Te-An Chen
IPC分类号: H01L21/8234 , H01L21/28 , H01L21/3115 , H01L21/768 , H01L23/64 , H01L27/06 , H01L27/08 , H01L29/92 , H01L49/02
CPC分类号: H01L28/40 , H01L21/823481 , H01L27/0629 , H01L27/0805 , H01L27/0811
摘要: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.
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公开(公告)号:US11935791B2
公开(公告)日:2024-03-19
申请号:US17855297
申请日:2022-06-30
发明人: Te-An Chen , Meng-Han Lin
IPC分类号: H01L21/8234 , B82Y10/00 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号: H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L27/0924 , H01L29/0847 , H01L29/7848 , H01L21/823814 , H01L29/42392
摘要: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.
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公开(公告)号:US11855080B2
公开(公告)日:2023-12-26
申请号:US17876536
申请日:2022-07-29
发明人: Meng-Han Lin , Te-An Chen
IPC分类号: H01L29/76 , H01L29/94 , H01L27/088 , H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/423
CPC分类号: H01L27/088 , H01L21/823462 , H01L21/823481 , H01L29/0649 , H01L29/42368 , H01L29/66545
摘要: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.
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公开(公告)号:US11854863B2
公开(公告)日:2023-12-26
申请号:US17357828
申请日:2021-06-24
发明人: Te-An Chen , Meng-Han Lin
IPC分类号: H01L21/762 , H01L21/765 , H01L27/088 , H01L29/40 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/02 , H01L29/165 , H01L29/78
CPC分类号: H01L21/76224 , H01L21/765 , H01L27/088 , H01L29/401 , H01L29/405 , H01L29/66636
摘要: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.
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公开(公告)号:US20220328472A1
公开(公告)日:2022-10-13
申请号:US17844078
申请日:2022-06-20
发明人: Meng-Han Lin , Te-An Chen
IPC分类号: H01L27/06 , H01L29/417 , H01L21/8234 , H01L29/06
摘要: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.
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