公开(公告)号：US20240387658A1

公开(公告)日：2024-11-21

申请号：US18783869

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US20240347598A1

公开(公告)日：2024-10-17

申请号：US18750589

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L29/0649 ,  H01L29/785 ,  H01L23/528

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.

公开(公告)号：US12021119B2

公开(公告)日：2024-06-25

申请号：US18358576

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L29/0649 ,  H01L29/785 ,  H01L23/528

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

公开(公告)号：US20240186179A1

公开(公告)日：2024-06-06

申请号：US18420209

申请日：2024-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/02603 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/5329 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US11862559B2

公开(公告)日：2024-01-02

申请号：US17337962

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate.

公开(公告)号：US11817491B2

公开(公告)日：2023-11-14

申请号：US16935061

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0653

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

公开(公告)号：US20230343854A1

公开(公告)日：2023-10-26

申请号：US17879529

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh SU ,  Lin-Yu Huang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

Abstract: A semiconductor device with air spacer structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, nanostructured channel regions disposed on the substrate, a gate structure surrounding the nanostructured channel regions, a first air spacer disposed on the gate structure, a source/drain (S/D) region disposed on the substrate, and a contact structure disposed on the S/D region. The contact structure includes a silicide layer disposed on the S/D region, a conductive layer disposed on the silicide layer, a dielectric layer disposed along a sidewall of the conductive layer, and a second air spacer disposed along a sidewall of the dielectric layer.

公开(公告)号：US11694921B2

公开(公告)日：2023-07-04

申请号：US17649503

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/763 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31144 ,  H01L27/0886

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US11670581B2

公开(公告)日：2023-06-06

申请号：US17104760

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53204 ,  H01L23/53209 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a source/drain (S/D) feature formed in an interlayer dielectric layer (ILD), a S/D contact via electrically connected to the S/D feature, a metal feature formed over the S/D contact via, and a metal line formed over the metal feature and electrically connected to the S/D contact via. The metal line is formed of a material different from that of the S/D contact via, and the S/D contact via is spaced apart from the metal line. By providing the metal feature, electromigration between the metal line and the contact via may be advantageously reduced or substantially eliminated.

公开(公告)号：US20230121408A1

公开(公告)日：2023-04-20

申请号：US18066071

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L23/532

Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.