公开(公告)号：US09159825B2

公开(公告)日：2015-10-13

申请号：US13860371

申请日：2013-04-10

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L21/683 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

摘要： A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

摘要翻译： 在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。 在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。 在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。 半导体层的一部分在第一表面被去除，暴露出新的第三表面。 第三掺杂区域形成在第三表面的半导体层的内部。 至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。 以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。

公开(公告)号：US20150287783A1

公开(公告)日：2015-10-08

申请号：US14746398

申请日：2015-06-22

申请人： SILANNA SEMICONDUCTOR U.S.A., INC.

发明人： Anton Arriagada ,  Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/268 ,  H01L21/762 ,  H01L21/304

CPC分类号： H01L29/0692 ,  H01L21/02365 ,  H01L21/2007 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/84 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803

摘要： A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

摘要翻译： 通过化学蚀刻和/或半导体层的表面的激光纹理来形成用于集成电路芯片的陷阱富集层。 在一些实施方案中，通过选自由激光纹理化学，化学蚀刻，照射，纳米腔形成，多孔硅蚀刻，半绝缘多晶硅，热应力释放和机械纹理组成的一组技术组成的技术形成陷阱富集层。 此外，可以使用这些技术中的两种或更多种的组合来形成富含阱的层。

公开(公告)号：US09153434B2

公开(公告)日：2015-10-06

申请号：US14478446

申请日：2014-09-05

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Chris N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L21/30 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/20 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

摘要： An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

摘要翻译： 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US20150102401A1

公开(公告)日：2015-04-16

申请号：US14576122

申请日：2014-12-18

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L27/12 ,  H01L29/732 ,  H01L29/744 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

摘要： A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

摘要翻译： 垂直半导体器件（例如垂直功率器件，IGBT器件，垂直双极晶体管，UMOS器件或GTO晶闸管）形成有有源半导体区域，其中已经制造了多个半导体结构以形成有源 器件，并且在其下方已经去除了衬底材料的至少一部分以隔离有源器件，以暴露用于底侧电连接的半导体结构中的至少一个并且增强散热。 半导体结构中的至少一个优选地与有源半导体区域的底侧的电极接触。

公开(公告)号：US08928068B2

公开(公告)日：2015-01-06

申请号：US13857136

申请日：2013-04-04

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L21/683

CPC分类号： H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

摘要： A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

摘要翻译： 垂直半导体器件（例如垂直功率器件，IGBT器件，垂直双极晶体管，UMOS器件或GTO晶闸管）形成有有源半导体区域，其中已经制造了多个半导体结构以形成有源 器件，并且在其下方已经去除了衬底材料的至少一部分以隔离有源器件，以暴露用于底侧电连接的半导体结构中的至少一个并且增强散热。 半导体结构中的至少一个优选地与有源半导体区域的底侧的电极接触。

公开(公告)号：US20140377908A1

公开(公告)日：2014-12-25

申请号：US14478446

申请日：2014-09-05

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Chris N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L21/306 ,  H01L21/265 ,  H01L21/768

CPC分类号： H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

摘要： An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

摘要翻译： 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US20140319698A1

公开(公告)日：2014-10-30

申请号：US14326304

申请日：2014-07-08

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber ,  Mark Drucker

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/2007 ,  H01L21/3221 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/13

摘要： A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.

摘要翻译： 半导体结构形成有第一和第二半导体晶片和再分配层。 第一半导体晶片形成有第一有源层和第一互连层。 第二半导体晶片形成有第二有源层和第二互连层。 第二半导体晶片被倒置并结合到第一半导体晶片，并且从第二半导体晶片去除衬底。 再分布层在第二半导体晶片的一侧重新分布电连接焊盘位置。 再分配层还通过第二有源层和第二互连层中的孔与第一互连层电接触。

公开(公告)号：US20150364597A1

公开(公告)日：2015-12-17

申请号：US14824491

申请日：2015-08-12

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L29/78 ,  H01L29/10

CPC分类号： H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

摘要： A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

摘要翻译： 在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。 在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。 在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。 半导体层的一部分在第一表面被去除，暴露出新的第三表面。 第三掺杂区域形成在第三表面的半导体层的内部。 至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。 以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。

公开(公告)号：US20150249056A1

公开(公告)日：2015-09-03

申请号：US14707998

申请日：2015-05-08

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Paul A. Nygaard ,  Michael A. Stuber

IPC分类号： H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L27/12

CPC分类号： H01L23/562 ,  H01L21/7624 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit.

摘要翻译： 在一个实施例中，公开了一种具有信号处理区域的集成电路。 集成电路包括从绝缘体上硅晶片上分离的绝缘体上硅芯片。 绝缘体上的芯片包括有源层，绝缘体层，衬底和强化层。 衬底由挖掘的衬底区域和支撑区域组成，支撑区域与绝缘体层接触。 挖掘区域覆盖集成电路的信号处理区域的大部分。

公开(公告)号：US20160035833A1

公开(公告)日：2016-02-04

申请号：US14855652

申请日：2015-09-16

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L29/10 ,  H01L27/12 ,  H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L21/84 ,  H01L25/00

CPC分类号： H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

摘要： An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

摘要翻译： 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。