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    Nonvolatile memory devices including memory planes and memory systems including the same
    1.
    发明授权
    Nonvolatile memory devices including memory planes and memory systems including the same 有权

    公开(公告)号：US11657858B2

    公开(公告)日：2023-05-23

    申请号：US17338097

    申请日：2021-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

    IPC: G11C7/10

    CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME
    2.
    发明申请
    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20210295884A1

    公开(公告)日：2021-09-23

    申请号：US17338097

    申请日：2021-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HYUN-JIN KIM ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

    IPC: G11C7/10

    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

    Resistive memory device and operation
    3.
    发明授权
    Resistive memory device and operation 有权
    电阻式存储器和操作

    公开(公告)号：US09437290B2

    公开(公告)日：2016-09-06

    申请号：US14631182

    申请日：2015-02-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Hyo-Jin Kwon ,  Hyun-Kook Park ,  Chi-Weon Yoon ,  Yeong-Taek Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0033 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007

    Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.

    Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08913430B2

    公开(公告)日：2014-12-16

    申请号：US13955103

    申请日：2013-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

    Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200168277A1

    公开(公告)日：2020-05-28

    申请号：US16432959

    申请日：2019-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

    SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME
    8.
    发明申请
    SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME 有权
    分离门型非易失性存储器件，具有嵌入式分离型非易失性存储器件的半导体器件及其形成方法

    公开(公告)号：US20130242659A1

    公开(公告)日：2013-09-19

    申请号：US13743445

    申请日：2013-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

    IPC: H01L29/788 ,  G11C16/04

    CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

    Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

    Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

    Nonvolatile memory devices including memory planes and memory systems including the same
    9.
    发明授权
    Nonvolatile memory devices including memory planes and memory systems including the same 有权

    公开(公告)号：US11037626B2

    公开(公告)日：2021-06-15

    申请号：US16432959

    申请日：2019-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  H01L27/115

    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

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