公开(公告)号：US20210295884A1

公开(公告)日：2021-09-23

申请号：US17338097

申请日：2021-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-JIN KIM ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

IPC: G11C7/10

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

公开(公告)号：US20160358655A1

公开(公告)日：2016-12-08

申请号：US15051896

申请日：2016-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-HOON NA ,  HYUN-JIN KIM ,  JEONG-DON IHM

IPC: G11C16/08 ,  H01L25/065 ,  G11C16/26 ,  H01L23/525 ,  G11C5/06 ,  H01L23/00 ,  G11C16/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/4402 ,  H01L23/50 ,  H01L23/5256 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48137 ,  H01L2224/48177 ,  H01L2225/06506 ,  H01L2924/00014 ,  H01L2924/1438 ,  H01L2224/45099

Abstract: A semiconductor package includes an external electrode, an interface chip, and a semiconductor chip. The interface chip includes an external interface pad bonded to the external electrode, a plurality of internal interface pads, and an interface circuit coupled between the external interface pad and the plurality of internal interface pads. The semiconductor chip includes a signal pad that is selectively bonded to one of the plurality of internal interface pads. The interface circuit activates a connection between a selected pad, which corresponds to a pad that is bonded to the signal pad among the plurality of internal interface pads, and the external interface pad, and deactivates connections between unselected pads, which correspond to pads that are not bonded to the signal pad among the plurality of internal interface pads, and the external interface pad.

Abstract translation: 半导体封装包括外部电极，接口芯片和半导体芯片。 接口芯片包括接合到外部电极的外部接口焊盘，多个内部接口焊盘以及耦合在外部接口焊盘和多个内部接口焊盘之间的接口电路。 半导体芯片包括选择性地结合到多个内部接口焊盘之一的信号焊盘。 接口电路激活所选择的焊盘之间的连接，所述焊盘对应于在多个内部接口焊盘之间被结合到信号焊盘的焊盘和外部接口焊盘，并且去激活未选择的焊盘之间的连接， 未被接合到多个内部接口焊盘中的信号焊盘和外部接口焊盘。

公开(公告)号：US20200258577A1

公开(公告)日：2020-08-13

申请号：US16752924

申请日：2020-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOO-WOONG LEE ,  HYUN-JIN KIM ,  JAE-YONG JEONG

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each including a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch transmits the data dumped by the data latch to a data I/O circuit. While the cache latch included in at least one of the plurality of first page buffers is performing a data transmit operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.