公开(公告)号：US11854979B2

公开(公告)日：2023-12-26

申请号：US17379000

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Min Joo Lee ,  Wan Don Kim ,  Hyeon Jin Shin ,  Hyun Bae Lee ,  Hyun Seok Lim

IPC: H01L23/532 ,  H10B12/00 ,  H01L21/768

CPC classification number: H01L23/53252 ,  H01L23/53276 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H01L21/76885

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

公开(公告)号：US12014988B2

公开(公告)日：2024-06-18

申请号：US17358752

申请日：2021-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Min Joo Lee ,  Wan Don Kim ,  Hyun Bae Lee

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53252

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

公开(公告)号：US11967630B2

公开(公告)日：2024-04-23

申请号：US17669859

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon Lee ,  Wan Don Kim ,  Jong Ho Park ,  Sang Jin Hyun

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/511 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

公开(公告)号：US10770560B2

公开(公告)日：2020-09-08

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk Yim ,  Kug Hwan Kim ,  Wan Don Kim ,  Jung Min Park ,  Jong Ho Park ,  Byoung Hoon Lee ,  Yong Ho Ha ,  Sang Jin Hyun ,  Hye Ri Hong

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20200176575A1

公开(公告)日：2020-06-04

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US12046556B2

公开(公告)日：2024-07-23

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US20240136416A1

公开(公告)日：2024-04-25

申请号：US18234596

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki Park ,  Sung Hwan Kim ,  Wan Don Kim ,  Heung Seok Ryu

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.

公开(公告)号：US20230026976A1

公开(公告)日：2023-01-26

申请号：US17592629

申请日：2022-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Young Noh ,  Eui Bok Lee ,  Wan Don Kim ,  Han Min Jang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes: a substrate; a first interlayer insulating layer on the substrate; a first wiring pattern in a first trench of the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second wiring pattern in a second trench of the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; a third wiring pattern in a third trench of the third interlayer insulating layer, and including a wiring barrier layer and a wiring filling layer, wherein the wiring filling layer contacts the third interlayer insulating layer; a via trench extending from the first wiring pattern to the third trench; and a via including a via barrier layer and a via filling layer. The via barrier layer is in the via trench. The via filling layer contacts the first wiring pattern and the wiring filling layer.

公开(公告)号：US11296196B2

公开(公告)日：2022-04-05

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US12087833B2

公开(公告)日：2024-09-10

申请号：US18380754

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.