公开(公告)号：US20240136416A1

公开(公告)日：2024-04-25

申请号：US18234596

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki Park ,  Sung Hwan Kim ,  Wan Don Kim ,  Heung Seok Ryu

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.

公开(公告)号：US20240234525A9

公开(公告)日：2024-07-11

申请号：US18234596

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki Park ,  Sung Hwan Kim ,  Wan Don Kim ,  Heung Seok Ryu

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.