公开(公告)号：US11854979B2

公开(公告)日：2023-12-26

申请号：US17379000

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Min Joo Lee ,  Wan Don Kim ,  Hyeon Jin Shin ,  Hyun Bae Lee ,  Hyun Seok Lim

IPC: H01L23/532 ,  H10B12/00 ,  H01L21/768

CPC classification number: H01L23/53252 ,  H01L23/53276 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H01L21/76885

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

公开(公告)号：US12014988B2

公开(公告)日：2024-06-18

申请号：US17358752

申请日：2021-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Min Joo Lee ,  Wan Don Kim ,  Hyun Bae Lee

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53252

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

公开(公告)号：US20220208679A1

公开(公告)日：2022-06-30

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/48

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US12046556B2

公开(公告)日：2024-07-23

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.