公开(公告)号：US12243815B2

公开(公告)日：2025-03-04

申请号：US17680507

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wandon Kim ,  Rakhwan Kim

IPC: H01L23/522 ,  H01L21/768 ,  H10D64/23

Abstract: A semiconductor device includes a front-end-of-line (FEOL) layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

公开(公告)号：US20220238439A1

公开(公告)日：2022-07-28

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12046556B2

公开(公告)日：2024-07-23

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US20230026976A1

公开(公告)日：2023-01-26

申请号：US17592629

申请日：2022-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Young Noh ,  Eui Bok Lee ,  Wan Don Kim ,  Han Min Jang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes: a substrate; a first interlayer insulating layer on the substrate; a first wiring pattern in a first trench of the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second wiring pattern in a second trench of the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; a third wiring pattern in a third trench of the third interlayer insulating layer, and including a wiring barrier layer and a wiring filling layer, wherein the wiring filling layer contacts the third interlayer insulating layer; a via trench extending from the first wiring pattern to the third trench; and a via including a via barrier layer and a via filling layer. The via barrier layer is in the via trench. The via filling layer contacts the first wiring pattern and the wiring filling layer.

公开(公告)号：US20250063814A1

公开(公告)日：2025-02-20

申请号：US18661872

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Rak Hwan Kim ,  Jong Min Baek

IPC: H01L27/118

Abstract: A semiconductor device includes a substrate; a first transistor on the substrate; a first contact on a source/drain pattern of the first transistor; a second transistor on the substrate; a second contact on a gate electrode of the second transistor; a first connecting structure that includes at least one first wiring and at least one first via that are alternately stacked on the first contact; a second connecting structure that includes at least one second wiring and at least one second via that are alternately stacked on the second contact; a first connecting via on the first connecting structure; a second connecting via on the second connecting structure; and a connecting wiring on the first connecting via and the second connecting via.

公开(公告)号：US11664310B2

公开(公告)日：2023-05-30

申请号：US17373573

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Donggon Yoo ,  Wandon Kim

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L29/0649 ,  H01L29/0847

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US20220208679A1

公开(公告)日：2022-06-30

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/48

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US12199038B2

公开(公告)日：2025-01-14

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US20240421090A1

公开(公告)日：2024-12-19

申请号：US18398370

申请日：2023-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seo Woo Nam ,  Eui Bok Lee

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a lower wiring structure, an upper interlayer insulating film on the lower wiring structure and including an upper wiring trench and an upper wiring structure in the upper wiring trench. The upper wiring structure includes an upper barrier structure, and an upper filling film on the upper barrier structure. The upper barrier structure includes side wall portions extending along side walls of the upper wiring trench, and a bottom portion extending along a bottom face of the upper wiring trench. The upper barrier structure includes an upper barrier film, and an upper liner film between the upper barrier film and the upper filling film. The side wall portions of the upper barrier structure include a two-dimensional material (2D material), and the bottom face of the upper barrier structure is free of the two-dimensional material.

公开(公告)号：US11728268B2

公开(公告)日：2023-08-15

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.