公开(公告)号：US20240421190A1

公开(公告)日：2024-12-19

申请号：US18624253

申请日：2024-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Heum Choi ,  Gi Woong Shim ,  Rak Hwan Kim ,  Do Sun Lee ,  Hyo Seok Choi

IPC: H01L29/06 ,  H01L23/532 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least a first side of the gate electrode on the active pattern, and a source/drain contact connected to the source/drain region on the first side of the gate electrode. The source/drain contact may include first, second, and third layers which are sequentially stacked, the first to third layers including the same metal, with each layer having a respective crystal orientation. The source/drain contact may include a first grain boundary at an interface between the first layer and the second layer, and a second grain boundary at an interface between the second layer and the third layer.

公开(公告)号：US11942427B2

公开(公告)日：2024-03-26

申请号：US17947282

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yong Yoo ,  Jong Jin Lee ,  Rak Hwan Kim ,  Eun-Ji Jung ,  Won Hyuk Hong

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/28568 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53257

Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.

公开(公告)号：US20180158781A1

公开(公告)日：2018-06-07

申请号：US15833041

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Ji Jung ,  Rak Hwan Kim ,  Byung Hee Kim ,  Young Hun Kim ,  Gyeong Yun Han

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/53209

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.

公开(公告)号：US11923426B2

公开(公告)日：2024-03-05

申请号：US17367988

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Won Kang ,  Tae-Yeol Kim ,  Jeong Ik Kim ,  Rak Hwan Kim ,  Jun Ki Park ,  Chung Hwan Shin

IPC: H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

公开(公告)号：US11881519B2

公开(公告)日：2024-01-23

申请号：US17826380

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu Cho ,  Rak Hwan Kim ,  Hyeok-Jun Son ,  Do Sun Lee ,  Won Keun Chung

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28132 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US10388563B2

公开(公告)日：2019-08-20

申请号：US15668029

申请日：2017-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rak Hwan Kim ,  Byung Hee Kim ,  Sang Bom Kang ,  Jong Jin Lee ,  Eun Ji Jung

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.

公开(公告)号：US12165916B2

公开(公告)日：2024-12-10

申请号：US17838740

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Keun Chung ,  Joon Gon Lee ,  Rak Hwan Kim ,  Chung Hwan Shin ,  Do Sun Lee ,  Nam Gyu Cho

IPC: H01L21/768

Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.

公开(公告)号：US11349007B2

公开(公告)日：2022-05-31

申请号：US17015296

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu Cho ,  Rak Hwan Kim ,  Hyeok-Jun Son ,  Do Sun Lee ,  Won Keun Chung

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20210090999A1

公开(公告)日：2021-03-25

申请号：US16892649

申请日：2020-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yong YOO ,  Jong Jin Lee ,  Rak Hwan Kim ,  Eun-Ji Jung ,  Won Hyuk Hong

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.

公开(公告)号：US20250063814A1

公开(公告)日：2025-02-20

申请号：US18661872

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Rak Hwan Kim ,  Jong Min Baek

IPC: H01L27/118

Abstract: A semiconductor device includes a substrate; a first transistor on the substrate; a first contact on a source/drain pattern of the first transistor; a second transistor on the substrate; a second contact on a gate electrode of the second transistor; a first connecting structure that includes at least one first wiring and at least one first via that are alternately stacked on the first contact; a second connecting structure that includes at least one second wiring and at least one second via that are alternately stacked on the second contact; a first connecting via on the first connecting structure; a second connecting via on the second connecting structure; and a connecting wiring on the first connecting via and the second connecting via.