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公开(公告)号：US10340358B2
公开(公告)日：2019-07-02
申请号：US15951639
申请日：2018-04-12
发明人： Sung In Suh , Hoon Joo Na , Min Woo Song , Byoung Hoon Lee , Chan Hyeong Lee , Hu Yong Lee , Sang Jin Hyun
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate, a first active pattern disposed on the substrate and spaced apart from the substrate, a gate insulating film which surrounds the first active pattern, a first work function adjustment film which surrounds the gate insulating film and includes carbon, and a first barrier film which surrounds the first work function adjustment film, in which a carbon concentration of the first work function adjustment film increases as it goes away from the first barrier film.
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公开(公告)号：US20190081152A1
公开(公告)日：2019-03-14
申请号：US15951639
申请日：2018-04-12
发明人： Sung In Suh , Hoon Joo Na , Min Woo Song , Byoung Hoon Lee , Chan Hyeong Lee , Hu Yong Lee , Sang Jin Hyun
CPC分类号： H01L29/4966 , H01L21/02164 , H01L21/28088 , H01L21/28167 , H01L21/28518 , H01L29/517 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate, a first active pattern disposed on the substrate and spaced apart from the substrate, a gate insulating film which surrounds the first active pattern, a first work function adjustment film which surrounds the gate insulating film and includes carbon, and a first barrier film which surrounds the first work function adjustment film, in which a carbon concentration of the first work function adjustment film increases as it goes away from. the first barrier film.
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公开(公告)号：US12062706B2
公开(公告)日：2024-08-13
申请号：US17503764
申请日：2021-10-18
发明人： Jae-Jung Kim , Sang Yong Kim , Byoung Hoon Lee , Chan Hyeong Lee
IPC分类号： H01L29/423 , H01L21/8234 , H01L21/8238 , H01L29/06
CPC分类号： H01L29/42392 , H01L21/823431 , H01L21/82345 , H01L21/823821 , H01L29/0673
摘要： A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.
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公开(公告)号：US11967630B2
公开(公告)日：2024-04-23
申请号：US17669859
申请日：2022-02-11
发明人： Byoung Hoon Lee , Wan Don Kim , Jong Ho Park , Sang Jin Hyun
IPC分类号： H01L29/51 , H01L29/423 , H01L29/49 , H01L29/775 , H01L29/786
CPC分类号： H01L29/511 , H01L29/42392 , H01L29/4966 , H01L29/518 , H01L29/775 , H01L29/78696
摘要： A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.
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公开(公告)号：US10770560B2
公开(公告)日：2020-09-08
申请号：US16214537
申请日：2018-12-10
发明人： Jeong Hyuk Yim , Kug Hwan Kim , Wan Don Kim , Jung Min Park , Jong Ho Park , Byoung Hoon Lee , Yong Ho Ha , Sang Jin Hyun , Hye Ri Hong
IPC分类号： H01L29/423 , H01L29/51 , H01L29/66 , H01L27/092 , H01L29/78 , H01L29/49
摘要： A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.
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公开(公告)号：US11949012B2
公开(公告)日：2024-04-02
申请号：US17114598
申请日：2020-12-08
发明人： Jong Ho Park , Wan Don Kim , Weon Hong Kim , Hyeon Jun Baek , Byoung Hoon Lee , Jeong Hyuk Yim , Sang Jin Hyun
IPC分类号： H01L29/78 , H01L27/088 , H01L29/49 , H01L29/51
CPC分类号： H01L29/78391 , H01L27/0886 , H01L29/4966 , H01L29/516
摘要： A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
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公开(公告)号：US11282939B2
公开(公告)日：2022-03-22
申请号：US16269712
申请日：2019-02-07
发明人： Byoung Hoon Lee , Wan Don Kim , Jong Ho Park , Sang Jin Hyun
IPC分类号： H01L29/51 , H01L29/786 , H01L29/423 , H01L29/49 , H01L29/775
摘要： A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.
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