Semiconductor devices having composite spacers containing different dielectric materials
    2.
    发明授权
    Semiconductor devices having composite spacers containing different dielectric materials 有权
    具有包含不同介电材料的复合间隔物的半导体器件

    公开(公告)号:US09275995B2

    公开(公告)日:2016-03-01

    申请号:US14543140

    申请日:2014-11-17

    Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

    Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件,其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域,其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

    Method for Fabricating Semiconductor Device
    3.
    发明申请
    Method for Fabricating Semiconductor Device 有权
    半导体器件制造方法

    公开(公告)号:US20140024192A1

    公开(公告)日:2014-01-23

    申请号:US13932047

    申请日:2013-07-01

    Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.

    Abstract translation: 一种半导体器件的制造方法,其特征在于,在基板上形成伪栅极图案和间隔物,该间隔物配置在伪栅极图案的侧壁上,通过去除间隔物,在伪栅极图案的两面形成气隙, 通过去除伪栅极图案,并且在暴露的基板上顺序地形成包括高k绝缘膜和金属栅电极的栅极绝缘膜。

Patent Agency Ranking