Imaging device and method for controlling imaging device

    公开(公告)号:US12051387B2

    公开(公告)日:2024-07-30

    申请号:US17910753

    申请日:2021-03-11

    CPC classification number: G09G5/006 G09G2340/02 G09G2370/047 G09G2370/12

    Abstract: To enable uncompressed RAW data to be appropriately transmitted from an imaging device to an external device. A transmission unit transmits uncompressed RAW data to an external device via a transmission path. In a case where the external device does not support the uncompressed RAW data, the control unit controls the transmission unit so as not to perform output processing for outputting the uncompressed RAW data to the transmission path. For example, the information reception unit receives identification information indicating that the external device supports the uncompressed RAW data from the external device via the transmission path.

    DISPLAY STREAM COMPRESSION (DCS) WITH BUILT-IN HIGH PASS FILTER

    公开(公告)号:US20240233629A1

    公开(公告)日:2024-07-11

    申请号:US18093693

    申请日:2023-01-05

    Inventor: Semin KOONG

    Abstract: Sharpening of images in organic light emitting diode (OLED) displays through high pass filtering of edge data and use of additional line memory in display stream compression (DSC) part of a display driving integrated circuit (DDIC) is described herein. A system according to examples may locate edge points of line data by computing a difference between prediction data and filtered data, and adjust (e.g., add or subtract weights) the prediction data by comparing the computed difference with a predefined threshold. In some examples, a Sobel filter may be used with an additional line memory in the display stream compression (DSC) to obtain improved edge information. In other examples, the display stream compression (DSC)'s flatness check function may be used to identify and/or confirm edge data before adding or subtracting weights.

    METHOD AND APPARATUS FOR MATCHED BUFFER DECOMPRESSION

    公开(公告)号:US20240087539A1

    公开(公告)日:2024-03-14

    申请号:US18516583

    申请日:2023-11-21

    Abstract: A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.

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