A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.