公开(公告)号：US09698021B2

公开(公告)日：2017-07-04

申请号：US14970105

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Joo Lee ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dong-Su Yoo ,  Soo-Jung Choi

IPC: H01L21/28 ,  H01L21/02 ,  C23C16/455 ,  C23C16/458

CPC classification number: H01L21/28194 ,  C23C16/45544 ,  C23C16/4584 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228

Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.

公开(公告)号：US08963227B2

公开(公告)日：2015-02-24

申请号：US14049570

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4966

Abstract: Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

Abstract translation: 制造半导体器件的方法包括在被分成第一区域和第二区域的衬底上形成包括高k电介质材料的栅极绝缘层; 在所述第二区域中的所述栅极绝缘层的第二部分上形成包括第一金属的扩散阻挡层; 在所述栅绝缘层和所述扩散阻挡层上形成扩散层; 以及将所述扩散层的元素扩散到所述第一区域中的所述栅极绝缘层的第一部分中。

公开(公告)号：US20160049478A1

公开(公告)日：2016-02-18

申请号：US14678331

申请日：2015-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Kyun Song ,  Weon-Hong Kim ,  Soo-Jung Choi ,  Yoon-Tae Hwang

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor device comprises forming a gate insulation layer on a substrate including a first region and a second region, forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate, removing the capping layer from the first region and the second region, forming a second gate conductive layer on the first region and the second region, nitriding the second gate conductive layer, and forming a third gate conductive layer on the second region.

Abstract translation: 一种制造半导体器件的方法包括在包括第一区域和第二区域的衬底上形成栅极绝缘层，在第一区域和第二区域上形成第一栅极导电层和覆盖层，并对衬底进行热处理， 从所述第一区域和所述第二区域移除所述覆盖层，在所述第一区域和所述第二区域上形成第二栅极导电层，氮化所述第二栅极导电层，以及在所述第二区域上形成第三栅极导电层。

公开(公告)号：US09023718B2

公开(公告)日：2015-05-05

申请号：US14165857

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Ho Do ,  Ha-Jin Lim ,  Weon-Hong Kim ,  Hoi-Sung Chung ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513

Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.

Abstract translation: 制造半导体器件的方法包括：在半导体衬底上形成外延层; 在所述外延层上形成具有第一厚度的覆盖层; 以及在氧气氛中氧化所述覆盖层以形成具有第二厚度的第一栅极介电层。

公开(公告)号：US20170033013A1

公开(公告)日：2017-02-02

申请号：US15152815

申请日：2016-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-hong Kim ,  Dong-su Yoo ,  Min-Joo Lee ,  Moon-Kyun Song ,  Soo-jung Choi

IPC: H01L21/8234 ,  H01L21/76 ,  H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/322 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/306 ,  H01L21/30

CPC classification number: H01L21/823431 ,  H01L21/02057 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/28158 ,  H01L21/3003 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/3221 ,  H01L21/3247 ,  H01L21/76 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7854

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

Abstract translation: 集成电路器件可以包括覆盖鳍状有源区的顶表面和相对侧壁的栅极绝缘层，覆盖栅绝缘层的栅电极和沿翅片形有源区和 栅极绝缘层。 集成电路器件的制造方法可以包括：形成覆盖预备翅片状有源区域的下部的绝缘层，通过使初步的翅片状有源区域的上部退火而形成具有外表面的翅片状有源区域，其具有增加的平滑度 在氢气氛中形成翅片形有源区，形成覆盖鳍状有源区的外表面的氢原子层。 可以形成栅绝缘层和栅电极以覆盖鳍状有源区的顶表面和相对侧壁。

公开(公告)号：US20160013107A1

公开(公告)日：2016-01-14

申请号：US14640058

申请日：2015-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Moon-Kyun Song

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/321 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.

Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法包括在其中形成包括沟槽的绝缘层。 该方法包括在沟槽中形成高k层。 此外，该方法包括在高k层上形成金属层，然后在第一温度下进行第一热处理，并在高于第一温度的第二温度下进行第二热处理。

公开(公告)号：US20140035050A1

公开(公告)日：2014-02-06

申请号：US14049570

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-Jin LIM ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4966

Abstract: Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

Abstract translation: 制造半导体器件的方法包括在被分成第一区域和第二区域的衬底上形成包括高k电介质材料的栅极绝缘层; 在所述第二区域中的所述栅极绝缘层的第二部分上形成包括第一金属的扩散阻挡层; 在所述栅绝缘层和所述扩散阻挡层上形成扩散层; 以及将所述扩散层的元素扩散到所述第一区域中的所述栅极绝缘层的第一部分中。

公开(公告)号：US09779996B2

公开(公告)日：2017-10-03

申请号：US15152815

申请日：2016-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-hong Kim ,  Dong-su Yoo ,  Min-Joo Lee ,  Moon-Kyun Song ,  Soo-jung Choi

IPC: H01L21/30 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/76 ,  H01L29/06 ,  H01L21/324 ,  H01L21/322 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/02057 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/28158 ,  H01L21/3003 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/3221 ,  H01L21/3247 ,  H01L21/76 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7854

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

公开(公告)号：US09218977B2

公开(公告)日：2015-12-22

申请号：US14015414

申请日：2013-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Hyung-Suk Jung

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L21/28185 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A fabricating method of a semiconductor device includes stacking a high-k dielectric film not containing silicon (Si) and an insulating film containing silicon (Si) on a substrate, and diffusing Si contained in the insulating film into the high-k dielectric film by annealing the substrate having the high-k dielectric film and the insulating film stacked thereon.

Abstract translation: 半导体器件的制造方法包括在基板上堆叠不含硅（Si）的高k电介质膜和含硅（Si）的绝缘膜，并且将包含在绝缘膜中的Si扩散到高k电介质膜中，由 退火具有高k电介质膜的基板和堆叠在其上的绝缘膜。

公开(公告)号：US09431515B2

公开(公告)日：2016-08-30

申请号：US14640058

申请日：2015-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Moon-Kyun Song

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/321 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.

Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法包括在其中形成包括沟槽的绝缘层。 该方法包括在沟槽中形成高k层。 此外，该方法包括在高k层上形成金属层，然后在第一温度下进行第一热处理，并在高于第一温度的第二温度下进行第二热处理。