公开(公告)号：US20250022713A1

公开(公告)日：2025-01-16

申请号：US18633627

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jinuk Byun ,  Hoyoung Kim ,  Hyunkyu Moon ,  Kiho Bae ,  Boun Yoon ,  Hojoon Lee ,  Seunghoon Choi

IPC: H01L21/304 ,  G06N3/04 ,  H01L21/66 ,  H01L21/67

Abstract: An offset data correction method includes measuring a measurement target that has undergone a chemical mechanical polishing (CMP) process, generating an offset correction model based on the measurement of the measurement target, and using the offset correction model, correcting measured data obtained from the measurement of the measurement target, wherein the offset correction model is trained by using the measured data and layout data of the measurement target as inputs.

公开(公告)号：US20250025981A1

公开(公告)日：2025-01-23

申请号：US18647240

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojoon Lee ,  Jinuk Byun ,  Joongsuk Oh ,  Seongryeol Kim ,  Younggu Kim ,  Seunghoon Choi ,  Jaemyung Choe

IPC: B24B37/005

Abstract: The present disclosure relates to devices, methods, and systems for transforming measurement data. An example device for transforming measurement data includes a communicator configured to receive first measurement data, the first measurement data including step height values on a semiconductor chip with a chemical mechanical polishing (CMP) process performed thereon, and to receive layout data comprising a layout included in the semiconductor chip, and a processor configured to, based on the layout data, transform the first measurement data to second measurement data, the second measurement data including step height values of the semiconductor chip with a metal deposited thereon.

公开(公告)号：US12052852B2

公开(公告)日：2024-07-30

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.

公开(公告)号：US12096610B2

公开(公告)日：2024-09-17

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.