公开(公告)号：US12052852B2

公开(公告)日：2024-07-30

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.

公开(公告)号：US12096610B2

公开(公告)日：2024-09-17

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.