公开(公告)号：US12052852B2

公开(公告)日：2024-07-30

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.

公开(公告)号：US20140061813A1

公开(公告)日：2014-03-06

申请号：US13902099

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheong-Sik Yu ,  Choel-Hwyi Bae ,  Ju-Youn Kim ,  Chang-Min Hong

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/1116

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, a first high-k dielectric film pattern on the first region, a second high-k dielectric film pattern on the second region and having the same thickness as the first high-k dielectric film pattern. First and second work function control film patterns are positioned on the high-k dielectric film patterns of the first region. Third and fourth work function control patterns are positioned on the high-k dielectric film pattern of the second region, the first work function control pattern being thicker than the third work function control pattern and the fourth work function control pattern being thicker than the second.

Abstract translation: 一种半导体器件包括：包括第一区域和第二区域的半导体衬底，第一区域上的第一高k电介质膜图案，第二区域上的第二高k电介质膜图案，并且具有与第一高度相同的厚度 -k电介质膜图案。 第一和第二功能控制膜图案位于第一区域的高k电介质膜图案上。 第三和第四工作功能控制图案位于第二区域的高k电介质膜图案上，第一工作功能控制图案比第三工作功能控制图案厚，第四工作功能控制图案比第二工件功能控制图案厚。

公开(公告)号：US12096610B2

公开(公告)日：2024-09-17

申请号：US17194995

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bum Hong ,  Heesung Shin ,  Hojoon Lee ,  Younghun Jung ,  Chang-Min Hong

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.

公开(公告)号：US09064732B2

公开(公告)日：2015-06-23

申请号：US13902099

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheong-Sik Yu ,  Choel-Hwyi Bae ,  Ju-Youn Kim ,  Chang-Min Hong

IPC: H01L21/70 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/1116

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, a first high-k dielectric film pattern on the first region, a second high-k dielectric film pattern on the second region and having the same thickness as the first high-k dielectric film pattern. First and second work function control film patterns are positioned on the high-k dielectric film patterns of the first region. Third and fourth work function control patterns are positioned on the high-k dielectric film pattern of the second region, the first work function control pattern being thicker than the third work function control pattern and the fourth work function control pattern being thicker than the second.

Abstract translation: 一种半导体器件包括：包括第一区域和第二区域的半导体衬底，第一区域上的第一高k电介质膜图案，第二区域上的第二高k电介质膜图案，并且具有与第一高度相同的厚度 -k电介质膜图案。 第一和第二功能控制膜图案位于第一区域的高k电介质膜图案上。 第三和第四工作功能控制图案位于第二区域的高k电介质膜图案上，第一工作功能控制图案比第三工作功能控制图案厚，第四工作功能控制图案比第二工件功能控制图案厚。

公开(公告)号：US08941183B2

公开(公告)日：2015-01-27

申请号：US13915306

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheong-Sik Yu ,  Choel-Hwyi Bae ,  Ju-Youn Kim ,  Chang-Min Hong

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: There is provided a semiconductor device comprising, at least one SRAM cell, wherein the SRAM cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (Tinv) of a gate stack of the pass-gate transistor is different from Tinv of a gate stack of the pull-up transistor and Tinv of a gate stack of the pull-down transistor.

Abstract translation: 提供了一种半导体器件，其包括至少一个SRAM单元，其中所述SRAM单元包括上拉晶体管，下拉晶体管和通过栅极晶体管，以及栅极的反型层厚度（Tinv） 栅极晶体管的堆叠不同于上拉晶体管的栅极叠层的Tinv和下拉晶体管的栅极堆叠的Tinv。

公开(公告)号：US20140061809A1

公开(公告)日：2014-03-06

申请号：US13915306

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheong-Sik Yu ,  Choel-Hwyi Bae ,  Ju-Youn Kim ,  Chang-Min Hong

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: There is provided a semiconductor device comprising, at least one SRAM cell, wherein the SRAM cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (Tinv) of a gate stack of the pass-gate transistor is different from Tinv of a gate stack of the pull-up transistor and Tinv of a gate stack of the pull-down transistor.

Abstract translation: 提供了一种半导体器件，其包括至少一个SRAM单元，其中所述SRAM单元包括上拉晶体管，下拉晶体管和通过栅极晶体管，以及栅极的反型层厚度（Tinv） 栅极晶体管的堆叠不同于上拉晶体管的栅极叠层的Tinv和下拉晶体管的栅极堆叠的Tinv。