公开(公告)号：US20240224487A1

公开(公告)日：2024-07-04

申请号：US18604195

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI-IL KIM ,  Jung-gun YOU ,  Gi-gwan PARK

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

公开(公告)号：US20170256645A1

公开(公告)日：2017-09-07

申请号：US15446322

申请日：2017-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yup CHUNG ,  Myung-yoon UM ,  Dong-ho CHA ,  Jung-gun YOU ,  Gi-gwan PARK

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/7854 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

公开(公告)号：US20180090585A1

公开(公告)日：2018-03-29

申请号：US15824083

申请日：2017-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin LIM ,  Gi-gwan PARK ,  Weon-hong KIM

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/785

Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.

公开(公告)号：US20170084711A1

公开(公告)日：2017-03-23

申请号：US15269001

申请日：2016-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin LIM ,  Gi-gwan PARK ,  Weon-hong KIM

IPC: H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/785

Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.

公开(公告)号：US20230343787A1

公开(公告)日：2023-10-26

申请号：US18216041

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan SUH ,  Gi-gwan PARK ,  Dong-woo KIM ,  Dong-suk SHIN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L29/165 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L27/092 ,  H01L21/823807

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20190319028A1

公开(公告)日：2019-10-17

申请号：US16453721

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan SUH ,  Gi-gwan PARK ,  Dong-woo KIM ,  Dong-suk SHIN

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20180331220A1

公开(公告)日：2018-11-15

申请号：US16028918

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun YOU ,  Gi-gwan PARK ,  Ki-il KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US20170186603A1

公开(公告)日：2017-06-29

申请号：US15372434

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-hun MOON ,  Yong-suk TAK ,  Gi-gwan PARK

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/02126 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28247 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.

公开(公告)号：US20250151385A1

公开(公告)日：2025-05-08

申请号：US19018870

申请日：2025-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-chan SUH ,  Gi-gwan PARK ,  Dong-woo KIM ,  Dong-suk SHIN

IPC: H10D84/85 ,  H10D30/67 ,  H10D62/10 ,  H10D62/40 ,  H10D62/822 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20210265503A1

公开(公告)日：2021-08-26

申请号：US17315818

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon LEE ,  Gi-gwan PARK ,  Tae-young KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/267 ,  H01L29/20 ,  H01L29/22 ,  H01L29/16 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.