公开(公告)号：US20220059532A1

公开(公告)日：2022-02-24

申请号：US17521011

申请日：2021-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Soo HONG ,  Jeong Yun LEE ,  Geum Jung SEONG ,  Jin Won LEE ,  Hyun Ho JUNG

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/66

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

公开(公告)号：US20230207628A1

公开(公告)日：2023-06-29

申请号：US18115913

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward CHO ,  Seung Soo HONG ,  Geum Jung SEONG ,  Seung Hun LEE ,  Jeong Yun LEE

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L21/02576 ,  H01L29/0649 ,  H01L27/0207 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/30604 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/7848 ,  H01L21/02579 ,  H01L27/0924 ,  H01L29/0869 ,  H10B10/12

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US20210280469A1

公开(公告)日：2021-09-09

申请号：US17328348

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20230238283A1

公开(公告)日：2023-07-27

申请号：US18118505

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42364 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/6656

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20200328207A1

公开(公告)日：2020-10-15

申请号：US16739357

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Soo HONG ,  Jeong Yun LEE ,  Geum Jung SEONG ,  Jin Won LEE ,  Hyun Ho JUNG

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/11

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

公开(公告)号：US20190326180A1

公开(公告)日：2019-10-24

申请号：US16460127

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20190288065A1

公开(公告)日：2019-09-19

申请号：US15992401

申请日：2018-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward CHO ,  Seung Soo HONG ,  Geum Jung SEONG ,  Seung Hun LEE ,  Jeong Yun LEE

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L27/11 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US20180138092A1

公开(公告)日：2018-05-17

申请号：US15718482

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.