公开(公告)号：US11889688B2

公开(公告)日：2024-01-30

申请号：US17509567

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Gihwan Kim ,  Chungki Min

IPC: H01L27/11556 ,  H10B41/27 ,  H01L29/66 ,  G11C5/02 ,  H01L25/07 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L25/074 ,  H01L29/66666 ,  H10B43/27

Abstract: A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.

公开(公告)号：US11744079B2

公开(公告)日：2023-08-29

申请号：US17473141

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Chang-Sun Hwang ,  Chungki Min

IPC: H01L23/535 ,  H10B43/50 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

公开(公告)号：US11417675B2

公开(公告)日：2022-08-16

申请号：US16903514

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Jang ,  Chang-Sun Hwang ,  Chungki Min ,  Kieun Seo ,  Jongheun Lim

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.

公开(公告)号：US09870950B2

公开(公告)日：2018-01-16

申请号：US15371646

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Ja-Eung Koo ,  Jong-Hyung Park ,  Ho-Young Kim ,  Leian Bartolome ,  Bo-Un Yoon ,  Hyoung-Bin Moon

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L28/00 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

公开(公告)号：US09023704B2

公开(公告)日：2015-05-05

申请号：US13801341

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Young Yoon ,  Chang-Sun Hwang ,  Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L27/14 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract translation: 一种制造半导体器件的方法包括形成覆盖形成在衬底上的翅片的预隔离层，所述预隔离层包括与所述翅片接触的下预分离层和不与所述翅片接触的上预隔离层 通过执行第一抛光工艺去除上部预隔离层的一部分，并且平坦化预隔离层，使得翅片的上表面和预隔离层的上表面共面，通过执行 用于去除上部预隔离层的剩余部分的第二抛光工艺。

公开(公告)号：US10821572B2

公开(公告)日：2020-11-03

申请号：US15926244

申请日：2018-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Hoon Jeong ,  Sang-Hak Lee ,  Geun-Kyu Choi ,  Chang-Sun Hwang ,  Tae-Young Kwon ,  Young-Sang Kim ,  Hyung-Kyu Jin ,  Jeong-Nam Han

IPC: B24B37/00 ,  B24B37/015 ,  B24B55/02 ,  B24B49/14 ,  B24B37/26

Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.

公开(公告)号：US08796127B2

公开(公告)日：2014-08-05

申请号：US13734306

申请日：2013-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseok Kim ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。

公开(公告)号：US20130237045A1

公开(公告)日：2013-09-12

申请号：US13734306

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeseok KIM ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。