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公开(公告)号:US11417675B2
公开(公告)日:2022-08-16
申请号:US16903514
申请日:2020-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiseok Jang , Chang-Sun Hwang , Chungki Min , Kieun Seo , Jongheun Lim
IPC: H01L27/11573 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L21/768 , H01L27/11582 , H01L23/535 , H01L27/1157
Abstract: A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.
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公开(公告)号:US20220028877A1
公开(公告)日:2022-01-27
申请号:US17204380
申请日:2021-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Changsun Hwang , Gihwan Kim , Hansol Seok , Jongheun Lim , Kiseok Jang
IPC: H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582
Abstract: An integrated circuit device includes a vertical stack of nonvolatile memory cells on a substrate, which are configured as a vertical NAND string of memory cells. This vertical stack of nonvolatile memory cells includes a plurality of gate patterns, which are spaced apart from each other by corresponding electrically insulating layers. A dummy mold structure is also provided on the substrate. The dummy mold structure includes a vertical stack of sacrificial layers, which are spaced apart from each other by corresponding electrically insulating layers. An insulation pattern is provided, which fills a dish-shaped recess in a first one of the sacrificial layers in the vertical stack of sacrificial layers. This insulation pattern has an upper surface that is coplanar with an upper surface of the first one of the sacrificial layers.
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