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公开(公告)号：US10128261B2
公开(公告)日：2018-11-13
申请号：US14613956
申请日：2015-02-04
发明人： Raghuveer S. Makala , Rahul Sharangpani , Sateesh Koka , Genta Mizuno , Naoki Takeguchi , Senaka Krishna Kanakamedala , George Matamis , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , H01L29/49 , H01L21/28 , H01L27/11563 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/768 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11568
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
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公开(公告)号：US09679906B2
公开(公告)日：2017-06-13
申请号：US14823274
申请日：2015-08-11
发明人： Zhenyu Lu , Johann Alsmeier , Daxin Mao , Wenguang Shi , Sateesh Koka , Raghuveer S. Makala , George Matamis , Yao-Sheng Lee , Chun Ge
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L27/11524 , H01L27/11556
CPC分类号： H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582
摘要： A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.
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公开(公告)号：US09627399B2
公开(公告)日：2017-04-18
申请号：US14808229
申请日：2015-07-24
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/1157 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/02
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.
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4.发明授权公开(公告)号：US09570460B2
公开(公告)日：2017-02-14
申请号：US14620674
申请日：2015-02-12
IPC分类号： H01L21/336 , H01L27/115 , H01L21/311 , H01L21/28 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02063 , H01L21/28273 , H01L21/28282 , H01L21/31116 , H01L21/31144 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.
摘要翻译： 制造半导体器件的方法包括在衬底上形成第一材料和第二材料的交替层的堆叠，蚀刻堆叠以在堆叠中形成至少一个开口，使得受损区域位于 所述至少一个开口在所述至少一个开口的侧壁上形成掩蔽层，同时所述至少一个开口的底表面未被掩蔽层覆盖，并且进一步蚀刻所述至少一个开口的底表面去除 受损区域。
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公开(公告)号：US09530791B1
公开(公告)日：2016-12-27
申请号：US14883966
申请日：2015-10-15
发明人： Yanli Zhang , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115
摘要： A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.
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6.发明授权Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack 有权具有阻塞电介质的三维存储器件具有增强的防止氟侵蚀的保护公开(公告)号：US09515079B2
公开(公告)日：2016-12-06
申请号：US14751922
申请日：2015-06-26
发明人： Sateesh Koka , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , Yao-Sheng Lee , George Matamis , Wei Zhao
IPC分类号： H01L27/115 , H01L21/223 , H01L21/02 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/02164 , H01L21/02178 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/02356 , H01L21/2236 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7883 , H01L29/792
摘要： Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.
摘要翻译： 提供了用于阻止或减少氟扩散的阻挡电介质结构和/或较厚的阻挡金属膜。 可以在延伸穿过电绝缘层和牺牲材料层的存储器堆叠结构中形成隔离电介质层作为存储膜的外层。 在通过去除牺牲材料层形成背面凹槽之后，可以例如通过等离子体处理或热处理将掺杂剂引入到阻挡介电层的物理暴露部分中，以形成可以减少或防止氟扩散的氮氧化硅区域。 或者或另外，可以在背面凹部中形成一组金属氧化物阻挡介电材料部分，以延迟或防止氟扩散。 为了最小化对形成在背面凹槽中的导电层的不利影响，阻挡电介质材料部分可以从用于形成背面凹槽的沟槽侧向凹入。
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公开(公告)号：US09496274B2
公开(公告)日：2016-11-15
申请号：US14264407
申请日：2014-04-29
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/105 , H01L21/02 , H01L27/112 , H01L27/06 , H01L27/10 , H01L29/66 , H01L29/792 , H01L21/306
CPC分类号： H01L27/11551 , H01L21/022 , H01L21/30604 , H01L27/0688 , H01L27/101 , H01L27/1052 , H01L27/1128 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7926
摘要： A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material.
摘要翻译： 存储器件包括具有延伸穿过堆叠的多个NAND串的材料层堆叠以及穿过堆叠的沟槽，该沟槽具有限定沟槽宽度的一对侧壁，所述沟槽的宽度从沟槽的顶部基本上恒定或减小， 在比第一深度更靠近沟槽底部的第一深度和第二深度之间增加第一深度并且沟槽具有覆盖至少沟槽侧壁的绝缘材料。 另外的实施例包括存储器件，其包括堆叠的材料层和限定在一对沟槽之间的有源存储器单元区域，并且在有源区域内，堆叠包括第一材料和第二材料的交替层，以及活性区域外 堆叠包括第一材料和第三材料的交替层。
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8.发明授权Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer 有权具有凹陷电介质侧壁的半导体结构及其通过各向同性蚀刻阻挡介电层来制造的方法公开(公告)号：US09478558B2
公开(公告)日：2016-10-25
申请号：US14600226
申请日：2015-01-20
发明人： Sateesh Koka , Senaka Kanakamedala , Raghuveer S. Makala , Rahul Sharangpani , Yanli Zhang , Yao-Sheng Lee , George Matamis
IPC分类号： H01L21/8238 , H01L27/115 , H01L21/28 , H01L29/788 , H01L21/311 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/6653 , H01L29/7883
摘要： A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.
摘要翻译： 第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。 具有底部开口的间隔物通过沉积保形材料层和各向异性蚀刻形成在第一阻挡介电层上。 存储器开口底部的第一阻挡介质层的水平部分可以通过各向同性的蚀刻工艺进行蚀刻，该过程使过蚀刻最小化到衬底中。 可以在存储器开口中顺序地形成可选的附加阻挡介质层，至少一个电荷存储元件，隧道电介质和半导体沟道，以提供三维存储堆叠。
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公开(公告)号：US09431409B2
公开(公告)日：2016-08-30
申请号：US14066788
申请日：2013-10-30
发明人： Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L29/76 , H01L27/115 , H01L21/764 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11551 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
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10.发明申请公开(公告)号：US20160225866A1
公开(公告)日：2016-08-04
申请号：US14751689
申请日：2015-06-26
发明人： Somesh Peri , Raghuveer S. Makala , Sateesh Koka , Yao-Sheng Lee , Johann Alsmeier , George Matamis
IPC分类号： H01L29/49 , H01L21/28 , H01L29/10 , H01L27/02 , H01L27/115
CPC分类号： H01L29/4966 , H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.
摘要翻译： 可以在每个存储器开口内形成记忆膜和半导体通道，该存储器开口延伸穿过包括交替的多个绝缘体层和牺牲材料层的堆叠。 在通过去除对绝缘体层选择性的牺牲材料层形成后侧凹槽之后，可以在每个后侧凹槽中形成金属阻挡材料部分。 可以在每个后侧凹部中形成含钼部分。 每个后侧凹部可以单独填充含钼部分，或者可以用含钼部分和包括钼以外的材料的金属材料部分的组合填充。
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