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    Three dimensional NAND device and method of making thereof
    4.
    发明授权
    Three dimensional NAND device and method of making thereof 有权
    三维NAND器件及其制造方法

    公开(公告)号：US09236396B1

    公开(公告)日：2016-01-12

    申请号：US14539307

    申请日：2014-11-12

    申请人： SanDisk Technologies, Inc.

    发明人： Sateesh Koka ,  Senaka Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  George Matamis ,  Wei Zhao

    IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49

    CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/495 ,  H01L29/517 ,  H01L29/7883

    摘要： A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.

    摘要翻译： 单片三维NAND串包括半导体沟道，半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，以及基本上平行于衬底的主表面延伸的多个控制栅电极。 NAND串还包括位于半导体通道和多个控制栅极电极之间的记忆膜，以及包含多个蛤状部分的阻挡电介质，每个蛤状部分具有通过垂直部分连接的两个水平部分。 NAND串还包括位于存储器膜和阻挡电介质的每个相应蛤状部分之间的多个分立的覆盖氧化硅段，其包含相应的控制栅电极。 多个覆盖氧化硅段中的每一个具有弯曲的上侧和下侧以及基本上直的垂直侧壁。

    Method of making a three dimensional NAND device
    5.
    发明授权
    Method of making a three dimensional NAND device 有权
    制造三维NAND器件的方法

    公开(公告)号：US09305849B1

    公开(公告)日：2016-04-05

    申请号：US14539372

    申请日：2014-11-12

    申请人： SanDisk Technologies, Inc.

    发明人： Masanori Tsutsumi ,  Shigehiro Fujino ,  Sateesh Koka ,  Senaka Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  George Matamis ,  Wei Zhao

    IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/8239 ,  H01L21/283 ,  H01L27/115 ,  H01L21/822

    CPC分类号： H01L21/8239 ,  H01L21/28282 ,  H01L21/8221 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

    摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的基本垂直于基板的主表面延伸的端部，基本上平行于基板的主表面延伸的多个控制栅电极，电荷存储材料 位于多个控制栅电极和半导体沟道之间的层，位于电荷存储材料层和半导体沟道之间的隧道电介质，以及包含多个蛤状部分的阻挡电介质，每个具有两个水平部分的垂直部分 一部分。 多个控制栅电极中的每一个至少部分地位于蛤状阻挡电介质中的开口中，以及多个分立的覆盖氧化物段，其嵌入部分电荷存储材料层的厚度并位于阻挡电介质 和电荷存储材料层。

    NAND memory strings and methods of fabrication thereof
    8.
    发明授权
    NAND memory strings and methods of fabrication thereof 有权
    NAND存储器串及其制造方法

    公开(公告)号：US09379132B2

    公开(公告)日：2016-06-28

    申请号：US14523287

    申请日：2014-10-24

    申请人： SanDisk Technologies, Inc.

    发明人： Sateesh Koka ,  Raghuveer S. Makala ,  Yanli Zhang ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Yao-Sheng Lee ,  George Matamis

    IPC分类号： G11C11/34 ,  H01L21/36 ,  H01L23/48 ,  H01L29/78 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

    摘要翻译： 制造单片三维存储器件的方法包括执行第一蚀刻以形成存储器开口和使用不同蚀刻工艺的第二蚀刻，以从存储器开口的底部去除半导体衬底的损坏部分。 使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。 另外的实施例包括提高存储器开口中的半导体沟道材料和底层半导体层之间的界面的质量，这可能被底部开口蚀刻损坏，包括通过从存储器的底表面的外延生长形成单晶半导体沟道材料 暴露于底部开口蚀刻的开口和/或氧化表面，并在形成沟道材料之前去除氧化的表面。 还公开了通过实施方式形成的单片三维存储器件。