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    Semiconductor memory device having unequal pitch vertical channel transistors used as selection transistors
    1.
    发明授权
    Semiconductor memory device having unequal pitch vertical channel transistors used as selection transistors 有权
    具有用作选择晶体管的不等间距的垂直沟道晶体管的半导体存储器件

    公开(公告)号：US09391120B2

    公开(公告)日：2016-07-12

    申请号：US14449417

    申请日：2014-08-01

    Applicant: SanDisk 3D LLC

    Inventor： Teruyuki Mine

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L21/8234 ,  H01L21/768

    CPC classification number: H01L27/249 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  H01L21/768 ,  H01L21/823487 ,  H01L27/101 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the three-dimensional memory structure includes forming one or two channels in a transistor body to provide a current to selected memory cells. Programming can initially use one channel and subsequently use two channels based on a programming progress. A method for fabricating a semiconductor device includes etching a gate conductor material so that shared and non-shared control gates have a common height.

    Abstract translation: 半导体器件包括一组选择晶体管，例如在具有沿垂直位线布置的电阻变化存储单元的三维存储器结构或堆叠中。 每个选择晶体管具有非共享控制栅极和共享控制栅极。 晶体管本体可具有不相等的间距和共同的高度。 一些晶体管体可以与垂直位线不对准，以将晶体管拟合到堆叠。 用于对三维存储器结构进行编程的方法包括在晶体管体中形成一个或两个通道以向选定的存储单元提供电流。 编程最初可以使用一个通道，随后根据编程进度使用两个通道。 一种用于制造半导体器件的方法包括蚀刻栅极导体材料，使得共享和非共享的控制栅极具有共同的高度。

    Methods of Forming Sidewall Gates
    3.
    发明申请
    Methods of Forming Sidewall Gates 有权
    形成侧壁闸门的方法

    公开(公告)号：US20150162338A1

    公开(公告)日：2015-06-11

    申请号：US14099084

    申请日：2013-12-06

    Applicant: SanDisk 3D LLC

    Inventor： Akira Nakada ,  Michiaki Sano ,  Naohito Yanagida ,  Teruyuki Mine

    IPC: H01L27/115 ,  H01L29/78

    CPC classification number: H01L27/115 ,  H01L21/2815 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

    Abstract translation: 形成用于垂直晶体管的侧壁栅极的方法包括在多晶硅沟道结构上沉积栅极介电层，以及在栅极电介质上沉积栅极多晶硅层。 然后将栅极多晶硅层回蚀刻形成分离的栅电极。 然后在栅电极之间形成填料部分，然后在其边被保护的同时从顶部向下蚀刻。

    Three-dimensional resistive random access memory containing self-aligned memory elements
    5.
    发明授权
    Three-dimensional resistive random access memory containing self-aligned memory elements 有权

    公开(公告)号：US10096654B2

    公开(公告)日：2018-10-09

    申请号：US14851296

    申请日：2015-09-11

    Applicant: SanDisk 3D LLC

    Inventor： Shin Kikuchi ,  Kazushi Komeda ,  Takuya Futase ,  Teruyuki Mine ,  Seje Takaki ,  Eiji Hayashi ,  Toshihide Tobitsuka

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.

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