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    RESISTIVE MEMORY DEVICE
    3.
    发明申请
    RESISTIVE MEMORY DEVICE 有权
    电阻式存储器件

    公开(公告)号：US20170032838A1

    公开(公告)日：2017-02-02

    申请号：US15151661

    申请日：2016-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79

    Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.

    Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别连接到多个第一信号线的多个存储器单元和彼此交叉的多个第二信号线。 第一写入驱动器被配置为提供写入电压以将数据写入存储器单元。 第二写入驱动器被配置为设置在存储单元阵列和第一写入驱动器之间，并且将基于写入电压产生的写入电流提供给从多个第一信号线中选择的第一信号线。

    MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    4.
    发明申请
    MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    存储器件及其操作方法

    公开(公告)号：US20160133323A1

    公开(公告)日：2016-05-12

    申请号：US14791636

    申请日：2015-07-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYO-JIN KWON ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/1673 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/72

    Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.

    Abstract translation: 一种用于操作存储器件的方法，该存储器件包括设置在多个第一信号线和多条第二信号线彼此交叉的区域中的多个存储单元。 该方法包括将初始电压施加到多个第一信号线，使施加有初始电压的多条第一信号线浮置，向多条第二信号线施加第二禁止电压，以及增加多个第一信号线的电压电平 的第一信号线通过在浮置的多个第一信号线之间的电容耦合和施加第二禁止电压的多个第二信号线之间的第一禁止电压电平。

    RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT
    6.
    发明申请
    RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT 有权
    电阻式存储器件及其运行方法降低泄漏电流

    公开(公告)号：US20160093376A1

    公开(公告)日：2016-03-31

    申请号：US14683269

    申请日：2015-04-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONG-KYU LEE ,  DAE-SEOK BYEON ,  YEONG-TAEK LEE ,  CHI-WEON YOON ,  HYUN-KOOK PARK ,  HYO-JIN KWON

    IPC: G11C13/00

    CPC classification number: G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078

    Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.

    Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。

    MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    存储器件及其操作方法

    公开(公告)号：US20160027510A1

    公开(公告)日：2016-01-28

    申请号：US14697244

    申请日：2015-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONG-KYU LEE ,  DAE-SEOK BYEON ,  YEONG-TAEK LEE ,  CHI-WEON YOON ,  HYUN-KOOK PARK ,  HYO-JIN KWON

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/10 ,  G11C2013/0092

    Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.

    Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择存储单元的第二信号线根据执行编程循环的次数而改变。

    RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    8.
    发明申请
    RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    电阻记忆体装置及其操作方法

    公开(公告)号：US20160196876A1

    公开(公告)日：2016-07-07

    申请号：US14979947

    申请日：2015-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YONG-KYU LEE ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON ,  CHI-WEON YOON

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C5/063 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.

    Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。 写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。 电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。 电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于 检测到的节点电压。

    RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE
    9.
    发明申请
    RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE 有权
    电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法

    公开(公告)号：US20160118114A1

    公开(公告)日：2016-04-28

    申请号：US14743488

    申请日：2015-06-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYO-JIN KWON ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069

    Abstract: A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.

    Abstract translation: 一种操作电阻式存储器件和包括电阻性存储器件的电阻式存储器系统的方法是用于包括多个位线和至少一个虚拟位线的电阻式存储器件。 操作电阻式存储器件的方法包括检测伴随第一命令的第一地址，产生用于偏置非选择线路的多个禁止电压，以及向第一伪位线提供从多个禁止中选择的第一禁止电压 基于检测到第一地址的结果的电压。

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