公开(公告)号：US20240162132A1

公开(公告)日：2024-05-16

申请号：US18384152

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangsoo KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48229 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15174 ,  H01L2924/182

Abstract: Provided is a semiconductor package including a semiconductor chip, a connection structure below the semiconductor chip and electrically connected to the semiconductor chip, and an external connection terminal below the connection structure, wherein the connection structure includes a first via array including a plurality of first vias in a first direction, a second via array above the first via array and including a plurality of second vias in the first direction, and a first pad between the first via array and the second via array and on upper surfaces of the plurality of the first vias, wherein the second via array is offset from the first via array in the first direction and does not overlap the first via array in a vertical direction.

公开(公告)号：US20250070029A1

公开(公告)日：2025-02-27

申请号：US18943201

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20250151280A1

公开(公告)日：2025-05-08

申请号：US18918694

申请日：2024-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suseong NOH ,  Kwangsoo KIM ,  Taeyoung KIM ,  Ilho MYEONG ,  Sanghyun PARK ,  Suhwan LIM

IPC: H10B43/40 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device including a peripheral circuit structure, a cell structure including gate electrodes and stacked on the peripheral circuit structure, the cell structure including a cell region, a connection region, and a peripheral circuit connection region, the cell structure, a plurality of channel structures extending in a vertical direction through the gate electrodes in the cell region, each of the plurality of channel structures including a first end portion close to the peripheral circuit structure and a second end portion opposite to the first end portion, and a common source layer connected to the second end portion of each of the channel structures in the cell region may be provided.

公开(公告)号：US20210125928A1

公开(公告)日：2021-04-29

申请号：US16885933

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20250052667A1

公开(公告)日：2025-02-13

申请号：US18754702

申请日：2024-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyoun KANG ,  Gideok KIM ,  Kwangsoo KIM ,  Wookrae KIM ,  Jaeseok SON ,  Eunjoo LEE ,  Soonhong Charles HWANG

IPC: G01N21/21 ,  G01N21/95 ,  G01N21/956

Abstract: An optical measurement apparatus includes a first light emitter configured to emit a first light on a surface of a sample, a second light emitter configured to emit a second light on the surface of the sample on which the first light is focused, a physical property detector configured to obtain physical property information of the sample by detecting a change in an amount of light of the second light due to a photothermal effect of the first light on the surface of the sample, and at least one structure detector configured to obtain structural information of the sample by detecting a reflected light of at least one of the first light and the second light that is reflected from the surface of the sample.

公开(公告)号：US20230231009A1

公开(公告)日：2023-07-20

申请号：US17950507

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangsoo KIM ,  Jinhee Cheon

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/66068

Abstract: A power semiconductor device includes a base semiconductor layer including impurities of a first conductivity type; a body portion provided on the base semiconductor layer and defined by a source trench, the body portion including a gate trench extending inwardly from an upper surface of the body portion; a gate electrode provided in the gate trench; a source electrode provided on the body portion and spaced apart from the gate electrode; and a drain electrode provided below the base semiconductor layer, wherein the body portion includes: a drift layer provided on the base semiconductor layer and including impurities of the first conductivity type; and a pair of shielding regions provided in the drift layer, spaced apart from each other in a horizontal direction, and spaced apart from the base semiconductor layer and the gate trench, the pair of shielding regions including impurities of a second conductivity type different from the first conductivity type.

公开(公告)号：US20220344267A1

公开(公告)日：2022-10-27

申请号：US17861700

申请日：2022-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20200185240A1

公开(公告)日：2020-06-11

申请号：US16509835

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookrae KIM ,  Kwangsoo KIM ,  Gwangsik PARK

IPC: H01L21/67 ,  H01L21/66 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G01N21/95 ,  G01N21/88

Abstract: An inspection apparatus includes a first optical module including a first light source configured to emit first light to a semiconductor structure, a second light source configured to emit second light different from the first light to a portion adjacent to a portion to which the first light is emitted in the semiconductor structure, a detector configured to detect the second light reflected toward the second light source, and a lock-in amplifier connected to the first optical module and the detector.