公开(公告)号：US20250098558A1

公开(公告)日：2025-03-20

申请号：US18828335

申请日：2024-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hajun SUNG ,  Minwoo CHOI ,  Youngjae KANG ,  Kiyeon YANG ,  Changseung LEE

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

Abstract: A chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY′bSec, wherein the chalcogenide-based memory material may have an ovonic threshold-switching (OTS) characteristic, and a threshold voltage of the chalcogenide-based memory material may change according to a polarity and an intensity of an applied voltage. In XaY′bSec, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ independently may be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. A memory device may include the chalcogenide-based memory material. An electronic apparatus may include the memory device.

公开(公告)号：US20230354725A1

公开(公告)日：2023-11-02

申请号：US18349433

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Dongho AHN ,  Changseung LEE

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8828 ,  H10B63/24 ,  H10B63/84 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8413

Abstract: A semiconductor apparatus may include a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.

公开(公告)号：US20230091136A1

公开(公告)日：2023-03-23

申请号：US17835508

申请日：2022-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Segab KWON ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a chalcogenide-based material, and a switching element and a memory device that include the same. The chalcogenide-based material includes: a chalcogenide material and a dopant. The chalcogenide material includes Ge, Sb, and Se. The dopant includes at least one metal or metalloid element selected from In, Al, Sr, and Si, an oxide of the metal or metalloid element, or a nitride of the metal or metalloid element.

公开(公告)号：US20220173316A1

公开(公告)日：2022-06-02

申请号：US17330950

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Dongho AHN ,  Changseung LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided is a semiconductor apparatus including a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.

公开(公告)号：US20170064839A1

公开(公告)日：2017-03-02

申请号：US15065488

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyub LEE ,  Yunsung Woo ,  Changseung LEE ,  Eunhyoung CHO

IPC: H05K3/02 ,  B23K26/384 ,  B23K26/0622 ,  H05K3/18

CPC classification number: B23K26/0622 ,  B23K26/0624 ,  B23K26/082 ,  B23K26/083 ,  B23K26/0853 ,  B23K26/0869 ,  B23K26/384 ,  B23K26/386 ,  B23K26/389 ,  H01L31/1884 ,  H05K3/0047 ,  H05K3/146 ,  H05K2201/0108 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/10128 ,  H05K2203/107

Abstract: A method of patterning holes includes placing a substrate on a stage of a laser system, the substrate having a graphene layer on a surface thereof, generating a pulse laser from the laser system, and forming a plurality of hole patterns spaced apart from each other on the graphene layer by irradiating the pulse laser while the graphene layer is in motion.

Abstract translation: 图案化孔的方法包括将基板放置在激光系统的台上，所述基板在其表面上具有石墨烯层，从激光系统产生脉冲激光，并且形成多个彼此间隔开的孔图案 石墨烯层通过在石墨烯层运动时照射脉冲激光器。

公开(公告)号：US20160133349A1

公开(公告)日：2016-05-12

申请号：US14808360

申请日：2015-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhyoung CHO ,  Inyong SONG ,  Changseung LEE ,  Chan KWAK ,  Jaekwan KIM ,  Jooho LEE ,  Jinyoung HWANG

IPC: H01B1/22 ,  D06M23/00 ,  C23F1/32 ,  D06M15/564

CPC classification number: H01B1/22 ,  B82Y10/00 ,  B82Y40/00 ,  C23F1/02 ,  C23F1/14 ,  C23F1/30 ,  C23F1/40 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01L29/0673 ,  H01L29/413 ,  H01L31/022466 ,  H01L33/42

Abstract: Example embodiments relate to a nanostructure including a conductive region and a nonconductive region, wherein the conductive region includes at least one first nanowire, and the nonconductive region includes at least one second nanowire that is at least partially sectioned, a method of preparing the nanostructure, and a panel unit including the nanostructure.

Abstract translation: 示例实施方案涉及包括导电区域和非导电区域的纳米结构，其中所述导电区域包括至少一个第一纳米线，并且所述非导电区域包括至少部分切割的至少一个第二纳米线，制备纳米结构的方法， 以及包括纳米结构的面板单元。

公开(公告)号：US20240324246A1

公开(公告)日：2024-09-26

申请号：US18594355

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Donggeon GU ,  Bonwon KOO ,  Jeonghee PARK ,  Hajun SUNG ,  Dongho AHN ,  Zhe WU ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841 ,  H10N70/8825 ,  H10N70/8828

Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.

公开(公告)号：US20240107778A1

公开(公告)日：2024-03-28

申请号：US18298642

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseung LEE ,  Kiyeon Yang ,  Youngjae Kang ,  Hajun Sung ,  Dongho Ahn

IPC: H10B63/10 ,  H10B63/00

CPC classification number: H10B63/10 ,  H10B63/24 ,  H10B63/80

Abstract: A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.

公开(公告)号：US20240032308A1

公开(公告)日：2024-01-25

申请号：US18478776

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/24 ,  G11C13/0004 ,  H10B61/10 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/24 ,  H10N70/25 ,  H10N70/063 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20210405498A1

公开(公告)日：2021-12-30

申请号：US17469189

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongyub LEE ,  Yongsung KIM ,  Jaekwan KIM ,  Changseung LEE

IPC: G02F1/21

Abstract: Provided are a multilayer thin-film structure and a phase shifting device using the same. The multilayer thin-film structure includes at least one crystallization preventing layer and at least one dielectric layer that are alternately stacked. The at least one crystallization preventing layer includes an amorphous material, and a thickness of the at least one crystallization preventing layer is less than a thickness of the at least one dielectric layer.