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    Field effect transistor having increased carrier mobility
    1.
    发明授权
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管的载流子迁移率增加

    公开(公告)号：US07923785B2

    公开(公告)日：2011-04-12

    申请号：US10643461

    申请日：2003-08-18

    申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

    Field effect transistor having increased carrier mobility
    2.
    发明申请
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管具有增加的载流子迁移率

    公开(公告)号：US20050040477A1

    公开(公告)日：2005-02-24

    申请号：US10643461

    申请日：2003-08-18

    申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC分类号： H01L29/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

    Semiconductor on insulator MOSFET having strained silicon channel
    3.
    发明授权
    Semiconductor on insulator MOSFET having strained silicon channel 有权
    具有应变硅沟道的半导体绝缘体MOSFET

    公开(公告)号：US06943087B1

    公开(公告)日：2005-09-13

    申请号：US10738529

    申请日：2003-12-17

    申请人： Qi Xiang ,  Jung-Suk Goo ,  James N. Pan ,  Ming Ren Lin

    发明人： Qi Xiang ,  Jung-Suk Goo ,  James N. Pan ,  Ming Ren Lin

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

    摘要： Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.

    摘要翻译： 在使用可移除的虚拟栅极工艺制造其它MOSFET元件以形成SOI MOSFET之后，将应变硅在MOSFET的沟道区的硅锗层中的沟槽中的电介质材料上生长。 MOSFET由虚拟栅极制造在位，虚拟栅极被去除，并且在沟道区域中形成沟槽。 电介质材料在沟槽中生长，然后从硅锗沟槽侧壁生长应变硅，以形成延伸穿过电介质材料的应变硅层。 硅锗侧壁对应变硅施加应变，并且电介质材料的存在允许应变硅作为薄的完全耗尽层生长。 然后通过镶嵌加工形成替换浇口。

    Silicon on insulator substrate having improved thermal conductivity and method of its formation
    6.
    发明授权
    Silicon on insulator substrate having improved thermal conductivity and method of its formation 有权
    绝缘体上硅衬底具有改进的导热性及其形成方法

    公开(公告)号：US07015078B1

    公开(公告)日：2006-03-21

    申请号：US10658668

    申请日：2003-09-09

    申请人： Qi Xiang ,  Jung-Suk Goo ,  James Pan

    发明人： Qi Xiang ,  Jung-Suk Goo ,  James Pan

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78603 ,  H01L21/76254 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78687

    摘要： A silicon on insulator (SOI) substrate includes a layer of silicon carbide beneath an insulating layer on which semiconductor devices are formed. The silicon carbide layer has a high thermal conductivity and provides beneficial dissipation of thermal energy generated by the devices. The SOI substrate may be formed by a bonding method. SOI MOSFET devices using the SOI substrate are also disclosed.

    摘要翻译： 绝缘体上硅（SOI）衬底包括在其上形成有半导体器件的绝缘层下方的碳化硅层。 碳化硅层具有高导热性，并提供由器件产生的热能的有益耗散。 SOI衬底可以通过接合方法形成。 还公开了使用SOI衬底的SOI MOSFET器件。

    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
    8.
    发明授权
    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
    形成厚应变硅层的方法和掺入厚应变硅层的半导体结构

    公开(公告)号：US06730576B1

    公开(公告)日：2004-05-04

    申请号：US10335447

    申请日：2002-12-31

    申请人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    发明人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    IPC分类号： H01L21762

    CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

    摘要翻译： 应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。 在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。 两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。 因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。 在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

    Method of fabricating an integrated circuit channel region
    9.
    发明授权
    Method of fabricating an integrated circuit channel region 有权
    制造集成电路通道区域的方法

    公开(公告)号：US07138302B2

    公开(公告)日：2006-11-21

    申请号：US10755763

    申请日：2004-01-12

    申请人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

    发明人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

    IPC分类号： H01L21/335 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8249 ,  H01L27/01

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842

    摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

    摘要翻译： 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。