公开(公告)号：US09236448B2

公开(公告)日：2016-01-12

申请号：US12231369

申请日：2008-09-02

申请人： Eunha Kim ,  Minh-Van Ngo

发明人： Eunha Kim ,  Minh-Van Ngo

IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L21/2815 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6653

摘要： In the present method of fabricating a semiconductor device, initially, a semiconductor substrate is provided. An oxide layer is provided on and in contact with the substrate, and a polysilicon layer is provided on and in contact with the oxide layer. A layer of photoresist is provided on the polysilicon layer, and the photoresist is patterned to provide a photoresist body, which is used as a mask to etch away polysilicon and oxide, forming a polysilicon element thereunder. The photoresist body is then removed. A nickel layer is provided on the resulting structure, and a reaction step is undertaken to provide that nickel diffuses into the exposed top and side portions of the polysilicon body, forming nickel silicide. After the reaction step, the remaining nickel is removed, and a chemical-mechanical polishing step is undertaken to remove nickel silicide so that a pair of nickel silicide bodies remain, separated by polysilicon. Using the nickel silicide bodies as masks, the polysilicon and oxide thereunder are etched away.

摘要翻译： 在本发明的制造半导体器件的方法中，首先提供半导体衬底。 氧化物层设置在衬底上并与衬底接触，并且多晶硅层设置在氧化物层上并与氧化物层接触。 在多晶硅层上提供一层光致抗蚀剂，并且将光致抗蚀剂图案化以提供光致抗蚀剂体，其用作掩模以去除多晶硅和氧化物，从而形成其下的多晶硅元件。 然后去除光致抗蚀剂体。 在所得结构上提供镍层，并且进行反应步骤以使镍扩散到多晶硅体的暴露的顶部和侧部，形成硅化镍。 在反应步骤之后，除去剩余的镍，并进行化学机械抛光步骤以除去硅化镍，使得一对硅化镍体保留，被多晶硅分离。 使用硅化镍体作为掩模，其后的多晶硅和氧化物被蚀刻掉。

公开(公告)号：US08202810B2

公开(公告)日：2012-06-19

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US20120038051A1

公开(公告)日：2012-02-16

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US08035153B2

公开(公告)日：2011-10-11

申请号：US12788177

申请日：2010-05-26

申请人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

发明人： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/11568

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

公开(公告)号：US07786003B1

公开(公告)日：2010-08-31

申请号：US11136569

申请日：2005-05-25

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07632706B2

公开(公告)日：2009-12-15

申请号：US11256558

申请日：2005-10-21

申请人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

发明人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

IPC分类号： H01L51/40

CPC分类号： H01L51/001 ,  C23C16/54 ,  H01J2237/3321 ,  H01L27/285

摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

摘要翻译： 公开了一种用于处理有机存储单元的系统和方法。 示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。 晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。 钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。 结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。 该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。

公开(公告)号：US20090140325A1

公开(公告)日：2009-06-04

申请号：US12340274

申请日：2008-12-19

申请人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

发明人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

IPC分类号： H01L29/792

CPC分类号： H01L27/11534 ,  H01L21/26506 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66507 ,  H01L29/78

摘要： A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.

摘要翻译： 提供一种形成电子器件的方法，其包括选择性地将离子注入到工件中，其中将离子注入到包括半导体材料的工件的第一区域中，而基本上没有离子注入工件的第二区域 其还包括半导体材料。 该方法还包括在选择性地注入之后，在第一区域和第二区域上沉积含金属膜，然后使含金属膜与半导体材料反应，以在第一区域内形成第一金属半导体膜，并且将第二金属 在第二区域内的半导体膜。 第一金属半导体膜具有第一厚度，第二金属半导体膜具有与第一厚度不同的第二厚度。

公开(公告)号：US07482217B1

公开(公告)日：2009-01-27

申请号：US11949637

申请日：2007-12-03

申请人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

发明人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

IPC分类号： H01L21/8238

CPC分类号： H01L27/11534 ,  H01L21/26506 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66507 ,  H01L29/78

摘要： A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.

摘要翻译： 提供一种形成电子器件的方法，其包括选择性地将离子注入到工件中，其中将离子注入到包括半导体材料的工件的第一区域中，而基本上没有离子注入工件的第二区域 其还包括半导体材料。 该方法还包括在选择性地注入之后，在第一区域和第二区域上沉积含金属膜，然后使含金属膜与半导体材料反应，以在第一区域内形成第一金属半导体膜，并且将第二金属 在第二区域内的半导体膜。 第一金属半导体膜具有第一厚度，第二金属半导体膜具有与第一厚度不同的第二厚度。

公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US20080108193A1

公开(公告)日：2008-05-08

申请号：US11593086

申请日：2006-11-06

申请人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

发明人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/76883 ,  H01L27/11521

摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

摘要翻译： 通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。 实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu， 例如，100℃至150℃