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    Forming metal-semiconductor films having different thicknesses within different regions of an electronic device
    1.
    发明授权
    Forming metal-semiconductor films having different thicknesses within different regions of an electronic device 有权
    在电子设备的不同区域内形成具有不同厚度的金属半导体膜

    公开(公告)号：US07880221B2

    公开(公告)日：2011-02-01

    申请号：US12340274

    申请日：2008-12-19

    申请人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

    发明人： Eunha Kim ,  Wen Yu ,  Minh-Van Ngo ,  Kyunghoon Min ,  Hiu-Yung Wong

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11534 ,  H01L21/26506 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66507 ,  H01L29/78

    摘要： A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.

    摘要翻译： 提供一种形成电子器件的方法，其包括选择性地将离子注入到工件中，其中将离子注入到包括半导体材料的工件的第一区域中，而基本上没有离子注入工件的第二区域 其还包括半导体材料。 该方法还包括在选择性地注入之后，在第一区域和第二区域上沉积含金属膜，然后使含金属膜与半导体材料反应，以在第一区域内形成第一金属半导体膜，并且将第二金属 在第二区域内的半导体膜。 第一金属半导体膜具有第一厚度，第二金属半导体膜具有与第一厚度不同的第二厚度。

    Dual charge storage node memory device and methods for fabricating such device
    2.
    发明授权
    Dual charge storage node memory device and methods for fabricating such device 有权
    双电荷存储节点存储器件及其制造方法

    公开(公告)号：US07915123B1

    公开(公告)日：2011-03-29

    申请号：US11408866

    申请日：2006-04-20

    申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

    摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

    摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

    Selective contact formation using masking and resist patterning techniques
    3.
    发明授权
    Selective contact formation using masking and resist patterning techniques 有权
    使用掩模和抗蚀剂图案化技术的选择性接触形成

    公开(公告)号：US07622389B1

    公开(公告)日：2009-11-24

    申请号：US11411353

    申请日：2006-04-25

    申请人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    发明人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    IPC分类号： H01L21/302

    CPC分类号： H01L27/11526 ,  H01L27/11548

    摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

    摘要翻译： 包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。 然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。 然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。 然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

    Selective silicide formation using resist etch back
    8.
    发明授权
    Selective silicide formation using resist etch back 有权
    使用抗蚀剂回蚀的选择性硅化物形成

    公开(公告)号：US08445372B2

    公开(公告)日：2013-05-21

    申请号：US12644457

    申请日：2009-12-22

    申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    IPC分类号： H01L21/285 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

    摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

    摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

    SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK
    9.
    发明申请
    SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK 有权
    选择性硅化物形成使用电阻蚀刻

    公开(公告)号：US20090111265A1

    公开(公告)日：2009-04-30

    申请号：US11924823

    申请日：2007-10-26

    申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

    摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

    摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

    Dual charge storage node memory device and methods for fabricating such device
    10.
    发明授权
    Dual charge storage node memory device and methods for fabricating such device 有权
    双电荷存储节点存储器件及其制造方法

    公开(公告)号：US08183623B2

    公开(公告)日：2012-05-22

    申请号：US13075047

    申请日：2011-03-29

    申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

    摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

    摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。