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    Dual power swing pipeline design with separation of combinational and sequential logics
    3.
    发明授权
    Dual power swing pipeline design with separation of combinational and sequential logics 有权

    公开(公告)号：US09628077B2

    公开(公告)日：2017-04-18

    申请号：US14638270

    申请日：2015-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Jing Xie ,  Yang Du

    IPC: H03K19/00 ,  H03K3/037 ,  H03K19/0175 ,  H01L25/065 ,  G06F1/32

    CPC classification number: H03K19/0021 ,  G06F1/3296 ,  H01L25/0657 ,  H03K3/037 ,  H03K19/017509 ,  Y02D10/172

    Abstract: A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

    Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
    5.
    发明授权
    Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods 有权
    具有石墨烯屏蔽的三维（3-D）集成电路（3DICS）及相关组件和方法

    公开(公告)号：US09536840B2

    公开(公告)日：2017-01-03

    申请号：US13765061

    申请日：2013-02-12

    Applicant: QUALCOMM Incorporated

    Inventor： Yang Du

    IPC: H01L23/552 ,  H01L23/373 ,  H01L27/06 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

    CPC classification number: H01L23/552 ,  H01L23/373 ,  H01L23/5225 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.

    Abstract translation: 公开了具有石墨烯屏蔽的三维（3-D）集成电路（3DIC）。 在某些实施例中，至少石墨烯层位于3DIC的两相邻层之间。 石墨烯层是由纯碳制成的片状层，至少一个原子厚度为原子排列成正六边形图案。 石墨烯层可以设置在3DIC中的任意数量的相邻层之间。 在示例性实施例中，石墨烯层在3DIC中的相邻层之间提供电磁干扰屏蔽，以减少层之间的串扰。 在其它示例性实施例中，石墨烯层可以设置在3DIC中，以提供将热量引导和散热到3DIC的周边区域的散热器。 在一些实施例中，石墨烯层被配置为提供EMI屏蔽和热屏蔽。

    Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits
    6.
    发明授权
    Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits 有权
    具有折叠块和3D集成电路的复制引脚的知识产权块设计

    公开(公告)号：US09483598B2

    公开(公告)日：2016-11-01

    申请号：US14617896

    申请日：2015-02-09

    Applicant: QUALCOMM Incorporated

    Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

    Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

    Abstract translation: 用于三维（3D）集成电路的知识产权（IP）块设计方法可以包括将具有一个或多个电路组件的至少一个二维（2D）块折叠到具有多个层的3D块中，其中， 折叠的2D块中的多个电路组件可以分布在3D块中的多个层中。 此外，一个或多个引脚可以跨越3D块中的多个层复制，并且一个或多个复制引脚可以使用放置在3D块内部的一个或多个块内穿通硅通孔（TSV）彼此连接 。

    MULTI-LEVEL CONVERSION FLIP-FLOP CIRCUITS FOR MULTI-POWER DOMAIN INTEGRATED CIRCUITS (ICs) AND RELATED METHODS
    7.
    发明申请
    MULTI-LEVEL CONVERSION FLIP-FLOP CIRCUITS FOR MULTI-POWER DOMAIN INTEGRATED CIRCUITS (ICs) AND RELATED METHODS 审中-公开
    多功能域集成电路（IC）的多级转换FLIP-FLOP电路及相关方法

    公开(公告)号：US20160285439A1

    公开(公告)日：2016-09-29

    申请号：US14669030

    申请日：2015-03-26

    Applicant: QUALCOMM Incorporated

    Inventor： Jing Xie ,  Yang Du

    IPC: H03K3/3562

    CPC classification number: H03K3/35625 ,  H03K3/356139 ,  H03K3/356156 ,  H03K3/356165 ,  H03K3/356191

    Abstract: Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.

    Abstract translation: 公开了用于多功率域集成电路（IC）的多电平转换触发器电路和相关方法。 触发器电路在更高电压域的锁存电路中将接收到的输入数据信号的表示锁存在较低电压域中，而不需要单独的电压电平移位器。 因此，插入损耗/延迟最小化，从而提高性能。 在某些方面，触发器电路采用栅极控制的数据控制晶体管来控制锁存电路的激活。 通过将输入数据信号耦合到数据控制晶体管的栅极，低电压域中的输入数据信号不直接锁存到锁存电路中。 相反，数据控制晶体管被配置为响应于时钟信号而激活锁存电路以锁存代表较低电压域中的输入数据信号的逻辑值的较高电压域中的电压。

    Monolithic three dimensional integration of semiconductor integrated circuits
    9.
    发明授权
    Monolithic three dimensional integration of semiconductor integrated circuits 有权
    半导体集成电路的单片三维集成

    公开(公告)号：US09177890B2

    公开(公告)日：2015-11-03

    申请号：US13788224

    申请日：2013-03-07

    Applicant: QUALCOMM Incorporated

    Inventor： Yang Du

    IPC: H01L29/06 ,  H01L23/48 ,  H01L29/775 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  B82Y10/00 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  B82Y99/00 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L23/48 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/76254 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

    Abstract: A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

    Abstract translation: 一种三维集成电路，包括形成在CMOS晶体管的底层上的顶层纳米线晶体管，具有层间通孔，层内通孔和金属层，以将各种CMOS晶体管和纳米线晶体管连接在一起。 顶层首先作为第一晶片上的轻掺杂区域开始，在该区域上形成氧化物层。 氢离子注入形成裂解界面。 第一晶片被翻转并且氧化物结合到具有CMOS器件的第二晶片，并且裂解界面被热激活，使得一部分轻掺杂区域保持结合到底层。 纳米线晶体管形成在顶层中。 顶层纳米线晶体管的源极和漏极通过在外延生长期间的原位掺杂形成。 在氧化物结合之后，剩余的工艺步骤在低温下进行，以免损坏金属互连。

    THREE-DIMENSIONAL (3D) MEMORY CELL SEPARATION AMONG 3D INTEGRATED CIRCUIT (IC) TIERS, AND RELATED 3D INTEGRATED CIRCUITS (3DICs), 3DIC PROCESSOR CORES, AND METHODS
    10.
    发明申请
    THREE-DIMENSIONAL (3D) MEMORY CELL SEPARATION AMONG 3D INTEGRATED CIRCUIT (IC) TIERS, AND RELATED 3D INTEGRATED CIRCUITS (3DICs), 3DIC PROCESSOR CORES, AND METHODS 有权
    3D集成电路（IC）TIER和相关3D集成电路（3DIC），3DIC处理器线和方法中的三维（3D）存储器单元分离

    公开(公告)号：US20150302919A1

    公开(公告)日：2015-10-22

    申请号：US14790510

    申请日：2015-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Jing Xie ,  Yang Du

    IPC: G11C11/419 ,  H01L27/06 ,  H01L21/768 ,  H01L23/48 ,  G11C5/02 ,  H01L27/11 ,  H01L23/522

    CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C11/419 ,  H01L21/768 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

    Abstract translation: 公开了3D集成电路（IC）（3DIC）层中的三维（3D）存储单元分离。 还公开了相关3DIC，3DIC处理器核心和方法。 在本文公开的实施例中，存储器块的存储器读取访问端口与3DIC的不同层级的存储器单元分离。 3DIC实现更高的器件封装密度，更低的互连延迟和更低的成本。 以这种方式，可以为读访问端口和存储单元提供不同的电源电压，以便能够降低读访问端口的电源电压。 结果可能会提供存储单元中的静态噪声容限和读/写噪声余量。 还可以避免增加面积的非分开的存储块内的多个电源轨。

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