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公开(公告)号：US10754653B2
公开(公告)日：2020-08-25
申请号：US14950612
申请日：2015-11-24
Applicant: QUALCOMM Incorporated
Inventor： Sergei Larin , Lucian Codrescu , Anshuman Das Gupta
Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.
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公开(公告)号：US20190196867A1
公开(公告)日：2019-06-27
申请号：US15983992
申请日：2018-05-18
Applicant: QUALCOMM Incorporated
Inventor： Erich Plondke , Suresh Kumar Venkumahanti , Lin Wang , Lucian Codrescu
IPC: G06F9/48
CPC classification number: G06F9/4818 , G06F9/4812 , G06F9/4881
Abstract: A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.
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公开(公告)号：US10114756B2
公开(公告)日：2018-10-30
申请号：US13828718
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Christopher Edward Koob , Erich James Plondke , Piyush Patel , Thomas Andrew Sartorius , Lucian Codrescu
IPC: G06F12/10 , G06F12/1009 , G06F12/109
Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
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4.发明申请公开(公告)号：US20180081687A1
公开(公告)日：2018-03-22
申请号：US15272613
申请日：2016-09-22
Applicant: QUALCOMM Incorporated
Inventor： Eric Mahurin , Lucian Codrescu
IPC: G06F9/30 , G06F9/38 , G06F12/0875 , G06F15/80
CPC classification number: G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/382 , G06F9/3834 , G06F9/3855 , G06F12/0875 , G06F15/8007 , G06F2212/452
Abstract: A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, multiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation.
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公开(公告)号：US09626579B2
公开(公告)日：2017-04-18
申请号：US14269380
申请日：2014-05-05
Applicant: QUALCOMM Incorporated
Inventor： Kim-Chyan Gan , Mao Zeng , Lucian Codrescu
CPC classification number: G06K9/46 , G06K9/4604 , G06K9/4609 , G06T1/20
Abstract: A method includes receiving image data and performing a non-maximum suppression (NMS) operation on the image data. The method also includes initiating an edge tracking by hysteresis (ETH) operation on a portion of the image data prior to completion of the NMS operation.
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Patent Agency Ranking
公开(公告)号：US09304932B2
公开(公告)日：2016-04-05
申请号：US13721317
申请日：2012-12-20
Applicant: QUALCOMM Incorporated
Inventor： Peter G. Sassone , Suresh K. Venkumahanti , Lucian Codrescu
CPC classification number: G06F12/0875 , G06F9/3802 , G06F9/3806 , G06F9/3832 , G06F12/0864 , G06F2212/6082 , Y02D10/13
Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.
Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩模的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的一个子集是响应于多位方式预测掩码启用的。 线路驱动器的子集包括多个线路驱动器。
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公开(公告)号：US20150317532A1
公开(公告)日：2015-11-05
申请号：US14269380
申请日：2014-05-05
Applicant: QUALCOMM Incorporated
Inventor： Kim-Chyan Gan , Mao Zeng , Lucian Codrescu
CPC classification number: G06K9/46 , G06K9/4604 , G06K9/4609 , G06T1/20
Abstract: A method includes receiving image data and performing a non-maximum suppression (NMS) operation on the image data. The method also includes initiating an edge tracking by hysteresis (ETH) operation on a portion of the image data prior to completion of the NMS operation.
Abstract translation: 一种方法包括接收图像数据并对图像数据执行非最大抑制（NMS）操作。 该方法还包括在完成NMS操作之前通过对图像数据的一部分的滞后（ETH）操作来启动边缘跟踪。
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公开(公告)号：US20140281368A1
公开(公告)日：2014-09-18
申请号：US13829503
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Ajay Anant Ingle , Lucian Codrescu , David J. Hoyle , Jose Fridman , Marc M. Hoffman , Deepak Mathew
IPC: G06F9/30
CPC classification number: G06F9/3853
Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.
Abstract translation: 用于在一个或多个时隙中执行多个指令的示例性方法包括接收包括多个指令的分组，并以时间共享的方式在一个或多个时隙中执行多个指令。 每个时隙与执行数据路径或存储器数据路径相关联。 用于执行多个阶段中的至少一个指令的示例性方法包括：接收包括指令的分组，将指令分解成多个阶段，以及执行多个阶段中的指令。
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公开(公告)号：US20140281332A1
公开(公告)日：2014-09-18
申请号：US13828718
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Christopher Edward Koob , Erich James Plondke , Piyush Patel , Thomas Andrew Sartorius , Lucian Codrescu
IPC: G06F12/10
CPC classification number: G06F12/10 , G06F12/1009 , G06F12/109 , G06F2212/1008 , G06F2212/1048 , G06F2212/1052 , G06F2212/657
Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
Abstract translation: 一种方法包括由处理器从存储设备或存储器管理单元读取一个或多个配置值。 该方法还包括将一个或多个配置值加载到处理器的一个或多个寄存器中。 一个或多个寄存器可由处理器执行地址转换。
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公开(公告)号：US09606818B2
公开(公告)日：2017-03-28
申请号：US13829023
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Erich James Plondke , Lucian Codrescu , Christopher Edward Koob , Piyush Patel , Thomas Andrew Sartorius
CPC classification number: G06F9/45533 , G06F9/5016 , G06F12/109 , G06F2212/1021 , G06F2212/151 , G06F2212/656
Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
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