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    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM
    2.
    发明申请
    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM 审中-公开
    在外围组件互连显式（PCIE）系统中交流交互特定属性

    公开(公告)号：US20160371221A1

    公开(公告)日：2016-12-22

    申请号：US15168574

    申请日：2016-05-31

    Applicant: QUALCOMM Incorporated

    Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

    IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

    CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2213/0026

    Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

    Abstract translation: 披露外围组件互连快递（PCIe）系统中的交易特定属性的通信。 PCIe系统包括主机系统和至少一个PCIe端点。 PCIe端点配置为确定可以提高预定义主机事务的效率和性能的一个或多个特定于事务的属性。 在这方面，在一方面，PCIe端点对至少一个PCIe TLP的事务层分组（TLP）前缀中的事务特定属性进行编码，并将PCIe TLP提供给主机系统。 在另一方面，主机系统中的PCIe根复合体（RC）被配置为从PCIe端点接收的PCIe TLP的TLP前缀中检测并提取特定于事务的属性。 通过传递PCIe TLP的TLP前缀中的特定于交易的属性，可以在不违反现有PCIe标准的情况下提高PCIe系统的效率和性能。

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    3.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 有权
    多重执行机构的系统与方法

    公开(公告)号：US20140282508A1

    公开(公告)日：2014-09-18

    申请号：US13829023

    申请日：2013-03-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Erich James Plondke ,  Lucian Codrescu ,  Christopher Edward Koob ,  Piyush Patel ,  Thomas Andrew Sartorius

    IPC: G06F9/455

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

    Translation of virtual addresses to physical addresses using translation lookaside buffer information
    4.
    发明授权
    Translation of virtual addresses to physical addresses using translation lookaside buffer information 有权

    公开(公告)号：US10754790B2

    公开(公告)日：2020-08-25

    申请号：US15964061

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Jason Norman ,  Piyush Patel ,  Rakesh Anigundi ,  Sadayan Ghows Ghani Sadayan Ebramsah Mo Abdul

    IPC: G06F12/1027

    Abstract: A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.

    Hardware co-ordination of resource management in distributed systems
    8.
    发明授权
    Hardware co-ordination of resource management in distributed systems 有权

    公开(公告)号：US11640317B2

    公开(公告)日：2023-05-02

    申请号：US16298419

    申请日：2019-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Piyush Patel ,  Kevin Mann ,  Theodore Haggis ,  Malvika Singh ,  Mit Kutchi

    IPC: G06F9/46 ,  G06F9/30 ,  G06F9/48 ,  G06F13/16 ,  G06F9/52 ,  G06F9/50 ,  G06F9/38

    Abstract: Systems and methods are directed to methods and apparatus for transferring ownership of common resources from a source entity, which owns a resource, to a destination entity, which will own the resource, in a distributed system. The method includes the source entity receiving a command to change ownership (the MOVE command), and then marking the source entity as no longer owning the common resource. The source entity then sends a MOVE command to the destination entity, which will then update its common resource ownership table to reflect that the ownership of the common resource has been transferred from the source entity to the destination entity. It is advantageous that the updating of ownership of the common resource in the source entity occur simultaneously with the dispatching of the MOVE command to the destination entity.

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