公开(公告)号：US11347667B2

公开(公告)日：2022-05-31

申请号：US16243698

申请日：2019-01-09

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Sharon Graif ,  Shaul Yohai Yifrach

IPC: G06F11/07 ,  G06F11/30 ,  G06F13/20 ,  G06F13/42 ,  G06F13/362

Abstract: The disclosure includes systems and methods for bus control. A method comprises receiving a data exchange request, wherein the data exchange request includes a data exchange tag that identifies a data exchange, splitting the data exchange into a plurality of fractional data transactions, providing one or more bus commands to a system bus, receiving, at the bus controller, one or more acceptance notifications indicating that the one or more of the plurality have been accepted by the system bus, assigning transaction identifiers (TIDs) corresponding to the one or more of the plurality of fractional data transactions, receiving one or more completion notifications indicating that the one or more of the plurality have been completed, determining that each of the plurality of fractional data transactions associated with the data exchange tag have been completed, and notifying the processor that the requested data exchange has been completed.

公开(公告)号：US10922252B2

公开(公告)日：2021-02-16

申请号：US15184124

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/24 ,  G06F13/42

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

公开(公告)号：US20170286314A1

公开(公告)日：2017-10-05

申请号：US15084886

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Shaul Yohai Yifrach ,  Thomas Zeng

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1027 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/683 ,  Y02D10/13

Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express (PCIe) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIe EP. In another aspect, the PCIe EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

公开(公告)号：US20160371222A1

公开(公告)日：2016-12-22

申请号：US15184181

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg

IPC: G06F13/42 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F13/4282 ,  G06F12/0828 ,  G06F12/1441 ,  G06F13/4022 ,  G06F15/167 ,  G06F21/00 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Coherency driven enhancements to a PCIe transaction layer are disclosed. In an exemplary aspect, a coherency agent is added to a PCIe system to support a relaxed consistency model for use of memory therein. In particular, endpoints can request ownership of portions of the memory to read from and write to the memory. The coherency agent assigns an address range including the requested portions. The requesting endpoint copies the contents of the memory corresponding to the assigned address range into local endpoint memory to perform read and write operations locally. The owning endpoint may provide an updated snapshot of the copied memory contents upon request. At completion of use of the copied memory contents, or upon request from the coherency agent, ownership of the address range reverts back to the root complex, and the endpoint sends the updated contents back to the address range in the system memory element.

Abstract translation: 公开了对PCIe事务层的一致性驱动增强。 在示例性方面，将一致性代理添加到PCIe系统以支持用于其中的存储器的松弛一致性模型。 特别地，端点可以请求存储器的部分的所有权从存储器读取和写入存储器。 一致性代理分配包括所请求部分的地址范围。 请求端点将对应于分配的地址范围的内存的内容复制到本地端点存储器中，以在本地执行读写操作。 所拥有的端点可以根据请求提供复制的存储器内容的更新的快照。 在完成使用复制的存储器内容时，或者根据来自一致性代理的请求，地址范围的所有权返回到根复合体，并且端点将更新的内容发送回系统存储器元件中的地址范围。

公开(公告)号：US20160371221A1

公开(公告)日：2016-12-22

申请号：US15168574

申请日：2016-05-31

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2213/0026

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

Abstract translation: 披露外围组件互连快递（PCIe）系统中的交易特定属性的通信。 PCIe系统包括主机系统和至少一个PCIe端点。 PCIe端点配置为确定可以提高预定义主机事务的效率和性能的一个或多个特定于事务的属性。 在这方面，在一方面，PCIe端点对至少一个PCIe TLP的事务层分组（TLP）前缀中的事务特定属性进行编码，并将PCIe TLP提供给主机系统。 在另一方面，主机系统中的PCIe根复合体（RC）被配置为从PCIe端点接收的PCIe TLP的TLP前缀中检测并提取特定于事务的属性。 通过传递PCIe TLP的TLP前缀中的特定于交易的属性，可以在不违反现有PCIe标准的情况下提高PCIe系统的效率和性能。

公开(公告)号：US11287842B2

公开(公告)日：2022-03-29

申请号：US16927657

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20200153593A1

公开(公告)日：2020-05-14

申请号：US16186961

申请日：2018-11-12

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Shaul Yohai Yifrach ,  Lior Amarilio

IPC: H04L5/00 ,  G06F13/42 ,  H04L29/08 ,  H04L12/823 ,  H04L12/861

Abstract: Systems and methods for reducing latency on long distance point-to-point links where the point-to-point link is a Peripheral Component Interconnect (PCI) express (PCIE) link that modifies a receiver to advertise infinite or unlimited credits. A transmitter sends packets to the receiver. If the receiver's buffers fill, the receiver, contrary to PCIE doctrine, drops the packet and returns a negative acknowledgement (NAK) packet to the transmitter. The transmitter, on receipt of the NAK packet, resends packets beginning with the one for which the NAK packet was sent. By the time these resent packets arrive, the receiver will have had time to manage the packets in the buffers and be ready to receive the resent packets.

公开(公告)号：US10089275B2

公开(公告)日：2018-10-02

申请号：US15168574

申请日：2016-05-31

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

公开(公告)号：US09998573B2

公开(公告)日：2018-06-12

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L12/28 ,  H04L29/06 ,  H04L12/741 ,  H04L12/749

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

公开(公告)号：US20160371208A1

公开(公告)日：2016-12-22

申请号：US15184124

申请日：2016-06-16

Applicant: QUALCOMM Incorporated

Inventor： Ofer Rosenberg ,  Amit Gil ,  James Lionel Panian ,  Piyush Patel ,  Shaul Yohai Yifrach

IPC: G06F13/24 ,  G06F13/42

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract translation: 公开了扩展消息信号中断（MSI）数据。 在一个方面，MSI比特被修改为包括系统级标识符。 在示例性方面，MSI消息数据的高16位被修改为系统级标识符。 通过在MSI消息数据内提供系统级标识符，中断控制器可以验证中断源。