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    Multi-core page table sets of attribute fields
    2.
    发明授权
    Multi-core page table sets of attribute fields 有权
    多核页面表属性字段集合

    公开(公告)号：US09436616B2

    公开(公告)日：2016-09-06

    申请号：US13888069

    申请日：2013-05-06

    Applicant: QUALCOMM Incorporated

    Inventor： Colin Christopher Sharp ,  Thomas Andrew Sartorius

    IPC: G06F12/00 ,  G06F12/10 ,  G06F12/14

    CPC classification number: G06F12/1009 ,  G06F12/145

    Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

    Abstract translation: 一种设备包括存储器，其存储包括第一页表条目的第一页表，其中第一页表条目还包括物理地址，与页表条目相关联的替代位置，以及与该页表项相关联的存储器的物理页 实际地址。 第一处理单元被配置为：读取第一页表条目，并从第一页表条目确定物理地址。 所述第二处理单元被配置为：从所述第一页表条目读取所述物理地址，从所述替代位置确定第二页属性数据，其中所述第二页属性数据定义所述第二页属性数据的第二页属性数据的物理页的一个或多个可访问性属性 处理单元，并且根据一个或多个可访问性属性访问与物理地址相关联的存储器的物理页面。

    Method and apparatus to save and restore system memory management unit (MMU) contexts
    3.
    发明授权
    Method and apparatus to save and restore system memory management unit (MMU) contexts 有权
    保存和恢复系统内存管理单元（MMU）上下文的方法和装置

    公开(公告)号：US09086813B2

    公开(公告)日：2015-07-21

    申请号：US13834380

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas M. Zeng ,  Azzedine Touzni ,  Thomas Andrew Sartorius

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/12 ,  G06T1/60

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/12 ,  G06T1/60

    Abstract: A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources.

    Abstract translation: 无线移动设备包括具有用于保存和恢复系统MMU转换上下文的系统存储器管理单元（MMU）的图形处理单元（GPU）。 系统MMU耦合到存储器和GPU。 系统MMU包括一组硬件资源。 硬件资源可以是上下文库，其中每个上下文库具有一组硬件寄存器。 系统MMU还包括硬件控制器，其被配置为恢复与由GPU的执行线程发布的内容的访问流相关联的硬件资源。 当与内容的访问流相关联的硬件资源不被存储在硬件资源之一内时，相关联的硬件资源可以从存储器恢复为物理硬件资源。

    METHODS AND APPARATUS FOR IMPROVING PERFORMANCE OF SEMAPHORE MANAGEMENT SEQUENCES ACROSS A COHERENT BUS
    4.
    发明申请
    METHODS AND APPARATUS FOR IMPROVING PERFORMANCE OF SEMAPHORE MANAGEMENT SEQUENCES ACROSS A COHERENT BUS 有权
    用于改善相邻总线之间扫描管理序列性能的方法和装置

    公开(公告)号：US20140310468A1

    公开(公告)日：2014-10-16

    申请号：US13933337

    申请日：2013-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Philip Speier ,  Eric F. Robinson ,  Jaya Prakash Subramaniam Ganasan ,  Thomas Andrew Sartorius ,  James Norris Dieffenderfer

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/173

    Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

    Abstract translation: 针对具有两个或多个处理器的多处理器描述技术，这增加了独占命令以独占状态取高速缓存行的机会，这导致执行存储排他时的性能提高。 读取优先排序的新总线操作被用作对请求主机可能存储到高速缓存行的其他高速缓存的提示，并且如果可能的话，其他高速缓存应该给排队。 在大多数情况下，这将导致其他主人员排队，并且请求主人将线独占。 在大多数情况下，两个或多个处理器不会同时对同一地址执行信号量管理序列。 因此，请求主机的负载排他能够在独占状态下取高速缓存行增加次数。

    MULTI-CORE PAGE TABLE SETS OF ATTRIBUTE FIELDS
    7.
    发明申请
    MULTI-CORE PAGE TABLE SETS OF ATTRIBUTE FIELDS 有权
    多核域页面集合

    公开(公告)号：US20140331023A1

    公开(公告)日：2014-11-06

    申请号：US13888069

    申请日：2013-05-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Colin Christopher Sharp ,  Thomas Andrew Sartorius

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/145

    Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

    Abstract translation: 一种设备包括存储器，其存储包括第一页表条目的第一页表，其中第一页表条目还包括物理地址，与页表条目相关联的替代位置，以及与该页表项相关联的存储器的物理页 实际地址。 第一处理单元被配置为：读取第一页表条目，并从第一页表条目确定物理地址。 所述第二处理单元被配置为：从所述第一页表条目读取所述物理地址，从所述替代位置确定第二页属性数据，其中所述第二页属性数据定义所述第二页属性数据的第二页属性数据的物理页的一个或多个可访问性属性 处理单元，并且根据一个或多个可访问性属性访问与物理地址相关联的存储器的物理页面。

    METHOD AND APPARATUS TO SAVE AND RESTORE SYSTEM MEMORY MANAGEMENT UNIT (MMU) CONTEXTS
    8.
    发明申请
    METHOD AND APPARATUS TO SAVE AND RESTORE SYSTEM MEMORY MANAGEMENT UNIT (MMU) CONTEXTS 有权
    保存和恢复系统内存管理单元（MMU）的方法和装置

    公开(公告)号：US20140282580A1

    公开(公告)日：2014-09-18

    申请号：US13834380

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Thomas M. Zeng ,  Azzedine Touzni ,  Thomas Andrew Sartorius

    IPC: G06F3/06

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/12 ,  G06T1/60

    Abstract: A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources.

    Abstract translation: 无线移动设备包括具有用于保存和恢复系统MMU转换上下文的系统存储器管理单元（MMU）的图形处理单元（GPU）。 系统MMU耦合到存储器和GPU。 系统MMU包括一组硬件资源。 硬件资源可以是上下文库，其中每个上下文库具有一组硬件寄存器。 系统MMU还包括硬件控制器，其被配置为恢复与由GPU的执行线程发布的内容的访问流相关联的硬件资源。 当与内容的访问流相关联的硬件资源不被存储在硬件资源之一内时，相关联的硬件资源可以从存储器恢复为物理硬件资源。

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    9.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 有权
    多重执行机构的系统与方法

    公开(公告)号：US20140282508A1

    公开(公告)日：2014-09-18

    申请号：US13829023

    申请日：2013-03-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Erich James Plondke ,  Lucian Codrescu ,  Christopher Edward Koob ,  Piyush Patel ,  Thomas Andrew Sartorius

    IPC: G06F9/455

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

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