公开(公告)号：US10114756B2

公开(公告)日：2018-10-30

申请号：US13828718

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Erich James Plondke ,  Piyush Patel ,  Thomas Andrew Sartorius ,  Lucian Codrescu

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/109

Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.

公开(公告)号：US20180217930A1

公开(公告)日：2018-08-02

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/128 ,  G06F2212/401 ,  G06F2212/621 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US20160239060A1

公开(公告)日：2016-08-18

申请号：US14622467

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Xufeng Chen ,  Robert Allan Lester ,  Manojkumar Pyla ,  Peixin Zhong

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

Abstract translation: 半导体器件的特征尺寸在每一代新一代继续下降。 较小的通道长度导致泄漏电流增加。 为了减少泄漏电流，在不活动期间，器件内部的一些电源域可能被断电（例如，电源崩溃）。 然而，当电力返回到折叠域时，其他电力域中的电路可能经历与重新配置到新供电域的通信信道相关联的显着处理开销。 在本公开中提供的是用于隔离功率域以促进柔性功率崩溃的示例性技术，同时更好地管理与重新建立数据连接相关联的处理开销。

公开(公告)号：US20140281332A1

公开(公告)日：2014-09-18

申请号：US13828718

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Edward Koob ,  Erich James Plondke ,  Piyush Patel ,  Thomas Andrew Sartorius ,  Lucian Codrescu

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/1009 ,  G06F12/109 ,  G06F2212/1008 ,  G06F2212/1048 ,  G06F2212/1052 ,  G06F2212/657

Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.

Abstract translation: 一种方法包括由处理器从存储设备或存储器管理单元读取一个或多个配置值。 该方法还包括将一个或多个配置值加载到处理器的一个或多个寄存器中。 一个或多个寄存器可由处理器执行地址转换。

公开(公告)号：US10198362B2

公开(公告)日：2019-02-05

申请号：US15426473

申请日：2017-02-07

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/08 ,  G06F12/128 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：US10102031B2

公开(公告)日：2018-10-16

申请号：US14866012

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier Gadelrab ,  Christopher Edward Koob ,  Simon Booth ,  Aris Balatsos ,  Johnny Jone Wai Kuan ,  Myil Ramkumar ,  Bhupinder Singh Pabla ,  Sean David Sweeney ,  George Patsilaras

IPC: G06F9/48 ,  G06F11/07 ,  G06F9/46

Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

公开(公告)号：US09858201B2

公开(公告)日：2018-01-02

申请号：US14626925

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Erich James Plondke ,  Jiajin Tu

IPC: G06F12/10 ,  G06F12/1027 ,  G06F11/07 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F12/1027 ,  G06F1/32 ,  G06F11/073 ,  G06F11/079 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/502 ,  G06F2212/684 ,  Y02D10/13

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

公开(公告)号：US09606818B2

公开(公告)日：2017-03-28

申请号：US13829023

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Erich James Plondke ,  Lucian Codrescu ,  Christopher Edward Koob ,  Piyush Patel ,  Thomas Andrew Sartorius

IPC: G06F9/455 ,  G06F9/46 ,  G06F7/04 ,  G06F21/00 ,  G06F9/50 ,  G06F12/10

CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

公开(公告)号：US10482021B2

公开(公告)日：2019-11-19

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Richard Senior ,  Anand Janakiraman

IPC: G06F12/0871 ,  G06F12/0868

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time.

公开(公告)号：US10169246B2

公开(公告)日：2019-01-01

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1036

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.